Assertion modelling using time delay

SystemVerilog
,
2

Problem Statement: When Signal A is de-asserted (from 0 to 1)
and within 700ns Signal B should be de-asserted (from 1 to 0).
This property should be re-usuable.


// minor corrected Code:
property delay (logic a,b, realtime delay);
        realtime t_v[2];
        @(posedge a)(1, t_var[0] = $realtime) ##0 @(negedge b)(1, t_v[1] = $realtime) ##0(t_v[1] - t_v[0]) <= delay;
    endproperty
       delay_s1    : assert property (@(posedge rst) delay(a_1, b_1, 700ns));
       delay_s2    : assert property (@(posedge rst) delay(a_2, b_2, 700ns));

Problem with the above code: Since i am using edge as my comparing some cases property fails incorrectly, how can I use a assert property for time delay based on level sensitivity.

I don’t understand the issue. Elaborate with an example.
Ben systemverilog.us