Index

$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · S · T · U · V · W · X · Y · Z

$#!
	+UVM_CONFIG_DB_TRACE uvm_cmdline_processor
	+UVM_DUMP_CMDLINE_ARGS uvm_cmdline_processor
	+UVM_MAX_QUIT_COUNT uvm_cmdline_processor
	+UVM_OBJECTION_TRACE uvm_cmdline_processor
	+UVM_PHASE_TRACE uvm_cmdline_processor
	+UVM_RESOURCE_DB_TRACE uvm_cmdline_processor
	+uvm_set_action uvm_cmdline_processor
	+uvm_set_config_int uvm_cmdline_processor
	+uvm_set_config_string uvm_cmdline_processor
	+uvm_set_default_sequence uvm_cmdline_processor
	+uvm_set_inst_override uvm_cmdline_processor
	+uvm_set_severity uvm_cmdline_processor
	+uvm_set_type_override uvm_cmdline_processor
	+uvm_set_verbosity uvm_cmdline_processor
	+UVM_TESTNAME uvm_cmdline_processor
	+UVM_TIMEOUT uvm_cmdline_processor
	+UVM_VERBOSITY uvm_cmdline_processor
	`uvm_add_to_sequence_library
	`uvm_analysis_imp_decl
	`uvm_blocking_get_imp_decl
	`uvm_blocking_get_peek_imp_decl
	`uvm_blocking_master_imp_decl
	`uvm_blocking_peek_imp_decl
	`uvm_blocking_put_imp_decl
	`uvm_blocking_slave_imp_decl
	`uvm_blocking_transport_imp_decl
	`uvm_component_end
	`uvm_component_param_utils
	`uvm_component_param_utils_begin
	`uvm_component_registry
	`uvm_component_utils
	`uvm_component_utils_begin
	`uvm_create
	`uvm_create_on
	`uvm_declare_p_sequencer
	`UVM_DEFAULT_TIMEOUT
	`uvm_do
	`uvm_do_callbacks
	`uvm_do_callbacks_exit_on
	`uvm_do_obj_callbacks
	`uvm_do_obj_callbacks_exit_on
	`uvm_do_on
	`uvm_do_on_pri
	`uvm_do_on_pri_with
	`uvm_do_on_with
	`uvm_do_pri
	`uvm_do_pri_with
	`uvm_do_with
	`uvm_error
	`uvm_error_begin
	`uvm_error_context
	`uvm_error_context_begin
	`uvm_error_context_end
	`uvm_error_end
	`uvm_fatal
	`uvm_fatal_begin
	`uvm_fatal_context
	`uvm_fatal_context_begin
	`uvm_fatal_context_end
	`uvm_fatal_end
	`uvm_field_*macro flags
	`uvm_field_*macros
	`uvm_field_aa_*_int macros
	`uvm_field_aa_*_string macros
	`uvm_field_aa_int_byte
	`uvm_field_aa_int_byte_unsigned
	`uvm_field_aa_int_enumkey
	`uvm_field_aa_int_int
	`uvm_field_aa_int_int_unsigned
	`uvm_field_aa_int_integer
	`uvm_field_aa_int_integer_unsigned
	`uvm_field_aa_int_key
	`uvm_field_aa_int_longint
	`uvm_field_aa_int_longint_unsigned
	`uvm_field_aa_int_shortint
	`uvm_field_aa_int_shortint_unsigned
	`uvm_field_aa_int_string
	`uvm_field_aa_object_int
	`uvm_field_aa_object_string
	`uvm_field_aa_string_string
	`uvm_field_array_*macros
	`uvm_field_array_enum
	`uvm_field_array_int
	`uvm_field_array_object
	`uvm_field_array_string
	`uvm_field_enum
	`uvm_field_event
	`uvm_field_int
	`uvm_field_object
	`uvm_field_queue_*macros
	`uvm_field_queue_enum
	`uvm_field_queue_int
	`uvm_field_queue_object
	`uvm_field_queue_string
	`uvm_field_real
	`uvm_field_sarray_*macros
	`uvm_field_sarray_enum
	`uvm_field_sarray_int
	`uvm_field_sarray_object
	`uvm_field_sarray_string
	`uvm_field_string
	`uvm_field_utils_begin
	`uvm_field_utils_end
	`uvm_get_imp_decl
	`uvm_get_peek_imp_decl
	`uvm_info
	`uvm_info_begin
	`uvm_info_context
	`uvm_info_context_begin
	`uvm_info_context_end
	`uvm_info_end
	`uvm_master_imp_decl
	`UVM_MAX_STREAMBITS
	`uvm_message_add_int
	`uvm_message_add_object
	`uvm_message_add_string
	`uvm_message_add_tag
	`uvm_nonblocking_get_imp_decl
	`uvm_nonblocking_get_peek_imp_decl
	`uvm_nonblocking_master_imp_decl
	`uvm_nonblocking_peek_imp_decl
	`uvm_nonblocking_put_imp_decl
	`uvm_nonblocking_slave_imp_decl
	`uvm_nonblocking_transport_imp_decl
	`uvm_object_param_utils
	`uvm_object_param_utils_begin
	`uvm_object_registry
	`uvm_object_utils
	`uvm_object_utils_begin
	`uvm_object_utils_end
	`uvm_pack_array
	`uvm_pack_arrayN
	`uvm_pack_enum
	`uvm_pack_enumN
	`uvm_pack_int
	`uvm_pack_intN
	`uvm_pack_queue
	`uvm_pack_queueN
	`uvm_pack_real
	`uvm_pack_sarray
	`uvm_pack_sarrayN
	`uvm_pack_string
	`UVM_PACKER_MAX_BYTES
	`uvm_peek_imp_decl
	`uvm_put_imp_decl
	`uvm_rand_send
	`uvm_rand_send_pri
	`uvm_rand_send_pri_with
	`uvm_rand_send_with
	`uvm_record_attribute
	`uvm_record_field
	`uvm_record_int
	`uvm_record_real
	`uvm_record_string
	`uvm_record_time
	`UVM_REG_ADDR_WIDTH
	`UVM_REG_BYTENABLE_WIDTH
	`UVM_REG_CVR_WIDTH
	`UVM_REG_DATA_WIDTH
	`uvm_register_cb
	`uvm_send
	`uvm_send_pri
	`uvm_sequence_library_utils
	`uvm_set_super_type
	`uvm_slave_imp_decl
	`UVM_TLM_B_MASK
	`UVM_TLM_B_TRANSPORT_IMP
	`UVM_TLM_FUNCTION_ERROR
	`UVM_TLM_NB_BW_MASK
	`UVM_TLM_NB_FW_MASK
	`UVM_TLM_NB_TRANSPORT_BW_IMP
	`UVM_TLM_NB_TRANSPORT_FW_IMP
	`UVM_TLM_TASK_ERROR
	`uvm_transport_imp_decl
	`uvm_unpack_array
	`uvm_unpack_arrayN
	`uvm_unpack_enum
	`uvm_unpack_enumN
	`uvm_unpack_int
	`uvm_unpack_intN
	`uvm_unpack_queue
	`uvm_unpack_queueN
	`uvm_unpack_real
	`uvm_unpack_sarray
	`uvm_unpack_sarrayN
	`uvm_unpack_string
	`uvm_warning
	`uvm_warning_begin
	`uvm_warning_context
	`uvm_warning_context_begin
	`uvm_warning_context_end
	`uvm_warning_end
0-9
	2 Migrating code using UVM 1
	2 Class Reference UVM 1
	2 Migration Script 1:: 1 to 1
	2 Release Notes UVM 1
	3? What will happen in UVM 1
A
	abstract uvm_comparer uvm_packer uvm_recorder
	abstractions uvm_reg_mem_hdl_paths_seq
	accept uvm_visitor_adapter#(STRUCTURE,uvm_visitor#(STRUCTURE))
	accept_tr uvm_component uvm_transaction
	Access uvm_reg uvm_reg_block uvm_reg_field uvm_reg_fifo
	Accessors uvm_link_base uvm_tlm_generic_payload
	Action Configuration uvm_report_object
	adapter uvm_reg_predictor uvm_reg_sequence
	add uvm_callbacks#(T,CB)uvm_heartbeat uvm_phase uvm_pool#(KEY,T)uvm_reg_read_only_cbs uvm_reg_write_only_cbs
	Add/ delete interface uvm_callbacks#(T,CB)
	add_by_name uvm_callbacks#(T,CB)
	add_callback uvm_event#(T)
	add_coverage uvm_mem uvm_reg uvm_reg_block
	add_hdl_path uvm_mem uvm_reg uvm_reg_block uvm_reg_file
	add_hdl_path_slice uvm_mem uvm_reg
	add_int uvm_report_catcher uvm_report_message uvm_report_message_element_container
	add_mem uvm_reg_map
	add_object uvm_report_catcher uvm_report_message uvm_report_message_element_container
	add_path uvm_hdl_path_concat
	add_reg uvm_reg_map
	add_sequence uvm_sequence_library
	add_sequences uvm_sequence_library
	add_slice uvm_hdl_path_concat
	add_string uvm_report_catcher uvm_report_message uvm_report_message_element_container
	add_submap uvm_reg_map
	add_typewide_sequence uvm_sequence_library
	add_typewide_sequences uvm_sequence_library
	add_uvm_phases uvm_domain
	addr uvm_reg_bus_op
	adjust_name uvm_printer
	after_export uvm_algorithmic_comparator#(BEFORE,AFTER,TRANSFORMER)uvm_in_order_comparator#(T,comp_type,convert,pair_type)
	Algorithmic Comparator
	all_dropped uvm_component uvm_objection uvm_objection_callback
	alloc_mode_e uvm_mem_mam
	allocate uvm_vreg
	Analysis Global uvm_tlm_if_base#(T1,T2)
	Analysis Ports
	analysis_export uvm_subscriber
	analysis_export#(T) uvm_tlm_analysis_fifo#(T)
	apply_config_settings uvm_component
	Argument Values uvm_cmdline_processor
	Attribute Recording uvm_recorder
	Audit Trail uvm_resource_base
B
	b_transport uvm_tlm_if
	Backawards Compatibility
	backdoor uvm_reg_map
	Backdoor uvm_mem uvm_reg uvm_reg_block uvm_reg_file
	backdoor_read uvm_mem uvm_reg
	backdoor_read_func uvm_mem uvm_reg
	backdoor_watch uvm_reg
	backdoor_write uvm_mem uvm_reg
	Backwards Compatibility
	Backwards Compatibility:
	BASE uvm_reg_sequence
	Basic Arguments uvm_cmdline_processor
	Basic Messaging Macros
	bd_kind uvm_reg_item
	before_export uvm_algorithmic_comparator#(BEFORE,AFTER,TRANSFORMER)uvm_in_order_comparator#(T,comp_type,convert,pair_type)
	begin_child_tr uvm_component uvm_transaction
	begin_elements uvm_printer_knobs
	begin_event uvm_transaction
	BEGIN_REQ
	BEGIN_RESP
	begin_tr uvm_component uvm_transaction
	begin_v uvm_visitor#(NODE)
	Bidirectional Interfaces&Ports
	big_endian uvm_packer
	bin_radix uvm_printer_knobs
	Bit Bashing Test Sequences
	Blocking get uvm_tlm_if_base#(T1,T2)
	Blocking peek uvm_tlm_if_base#(T1,T2)
	Blocking put uvm_tlm_if_base#(T1,T2)
	Blocking transport uvm_tlm_if_base#(T1,T2)
	blocking_put_port uvm_random_stimulus#(T)
	body uvm_mem_access_seq uvm_mem_single_walk_seq uvm_mem_walk_seq uvm_reg_access_seq uvm_reg_bit_bash_seq uvm_reg_hw_reset_seq uvm_reg_mem_built_in_seq uvm_reg_mem_shared_access_seq uvm_reg_sequence uvm_sequence_base
	build_coverage uvm_mem uvm_reg uvm_reg_block
	build_phase uvm_component
	Built-in UVM Aware Command Line Arguments uvm_cmdline_processor
	burst_read uvm_mem uvm_mem_region
	burst_write uvm_mem uvm_mem_region
	Bus Access uvm_reg_map
	bus_in uvm_reg_predictor
	bus2reg uvm_reg_adapter uvm_reg_tlm_adapter
	byte_en uvm_reg_bus_op

+UVM_CONFIG_DB_TRACE turns on tracing of configuration DB access.

+UVM_DUMP_CMDLINE_ARGS allows the user to dump all command line arguments to the reporting mechanism.

+UVM_MAX_QUIT_COUNT=<count>,<overridable> allows users to change max quit count for the report server.

+UVM_OBJECTION_TRACE turns on tracing of objection activity.

+UVM_PHASE_TRACE turns on tracing of phase executions.

+UVM_RESOURCE_DB_TRACE turns on tracing of resource DB access.

+uvm_set_action=<comp>,<id>,<severity>,<action> provides the equivalent of various uvm_report_object’s set_report_*_action APIs.

+uvm_set_config_int=<comp>,<field>,<value> and +uvm_set_config_string=<comp>,<field>,<value> work like their procedural counterparts: set_config_int() and set_config_string().

The +uvm_set_default_sequence=<seqr>,<phase>,<type> plusarg allows the user to define a default sequence from the command line, using the typename of that sequence.

+uvm_set_severity=<comp>,<id>,<current severity>,<new severity> provides the equivalent of the various uvm_report_object’s set_report_*_severity_override APIs.

+uvm_set_inst_override=<req_type>,<override_type>,<full_inst_path> and +uvm_set_type_override=<req_type>,<override_type>[,<replace>] work like the name based overrides in the factory--factory.set_inst_override_by_name() and factory.set_type_override_by_name().

+uvm_set_verbosity=<comp>,<id>,<verbosity>,<phase> and +uvm_set_verbosity=<comp>,<id>,<verbosity>,time,<time> allow the users to manipulate the verbosity of specific components at specific phases (and times during the “run” phases) of the simulation.

+UVM_TESTNAME=<class name> allows the user to specify which uvm_test (or uvm_component) should be created via the factory and cycled through the UVM phases.

+UVM_TIMEOUT=<timeout>,<overridable> allows users to change the global timeout of the UVM framework.

+UVM_VERBOSITY=<verbosity> allows the user to specify the initial verbosity for all components.

Adds the given sequence TYPE to the given sequence library LIBTYPE

uvm_component-based class declarations may contain one of the above forms of utility macros.

Registers a uvm_component-based class with the factory

This macro is used to declare a variable p_sequencer whose type is specified by SEQUENCER.

The default timeout for simulation, if not overridden by uvm_root::set_timeout or uvm_cmdline_processor::+UVM_TIMEOUT

Calls uvm_report_error with a verbosity of UVM_NONE.

This macro pair operates identically to `uvm_info_begin/`uvm_info_end with exception that the message severity is UVM_ERROR and has no verbosity threshold.

Calls uvm_report_fatal with a verbosity of UVM_NONE.

This macro pair operates identically to `uvm_info_begin/`uvm_info_end with exception that the message severity is UVM_FATAL and has no verbosity threshold.

Defines what operations a given field should be involved in.

Macros that implement data operations for scalar properties.

Macros that implement data operations for associative arrays indexed by an integral type.

Macros that implement data operations for associative arrays indexed by string.

Implements the data operations for an associative array of integral types indexed by the byte data type.

Implements the data operations for an associative array of integral types indexed by the byte unsigned data type.

Implements the data operations for an associative array of integral types indexed by any enumeration key data type.

Implements the data operations for an associative array of integral types indexed by the int data type.

Implements the data operations for an associative array of integral types indexed by the int unsigned data type.

Implements the data operations for an associative array of integral types indexed by the integer data type.

Implements the data operations for an associative array of integral types indexed by the integer unsigned data type.

Implements the data operations for an associative array of integral types indexed by any integral key data type.

Implements the data operations for an associative array of integral types indexed by the longint data type.

Implements the data operations for an associative array of integral types indexed by the longint unsigned data type.

Implements the data operations for an associative array of integral types indexed by the shortint data type.

Implements the data operations for an associative array of integral types indexed by the shortint unsigned data type.

Implements the data operations for an associative array of integrals indexed by string.

Implements the data operations for an associative array of uvm_object-based objects indexed by the int data type.

Implements the data operations for an associative array of uvm_object-based objects indexed by string.

Implements the data operations for an associative array of strings indexed by string.

Macros that implement data operations for one-dimensional dynamic array properties.

Implements the data operations for a one-dimensional dynamic array of enums.

Implements the data operations for a one-dimensional dynamic array of integrals.

Implements the data operations for a one-dimensional dynamic array of uvm_object-based objects.

Implements the data operations for a one-dimensional dynamic array of strings.

Implements the data operations for an enumerated property.

Implements the data operations for an event property.

Implements the data operations for any packed integral property.

Implements the data operations for a uvm_object-based property.

Macros that implement data operations for dynamic queues.

Implements the data operations for a one-dimensional queue of enums.

Implements the data operations for a queue of integrals.

Implements the data operations for a queue of uvm_object-based objects.

Implements the data operations for a queue of strings.

Implements the data operations for any real property.

Macros that implement data operations for one-dimensional static array properties.

Implements the data operations for a one-dimensional static array of enums.

Implements the data operations for a one-dimensional static array of integrals.

Implements the data operations for a one-dimensional static array of uvm_object-based objects.

Implements the data operations for a one-dimensional static array of strings.

Implements the data operations for a string property.

These macros form a block in which `uvm_field_* macros can be placed.

Calls uvm_report_info if VERBOSITY is lower than the configured verbosity of the associated reporter.

This macro pair provides the ability to add elements to messages.

Defines the maximum bit vector size for integral types.

These macros allow the user to provide elements that are associated with uvm_report_messages.

uvm_object-based class declarations may contain one of the above forms of utility macros.

Pack a dynamic array without having to also specify the bit size of its elements.

Pack a dynamic array of integrals.

Pack an enumeration value.

Pack an integral variable.

Pack an integral variable without having to also specify the bit size.

Pack an integral variable.

Pack a queue without having to also specify the bit size of its elements.

Pack a queue of integrals.

Pack a variable of type real.

Pack a static array without having to also specify the bit size of its elements.

Pack a static array of integrals.

Pack a string variable.

Defines the maximum bytes to allocate for packing an object using the uvm_packer.

Vendor-independent macro to hide tool-specific interface for recording attributes (fields) to a transaction database.

Macro for recording arbitrary name-value pairs into a transaction recording database.

Maximum address width in bits

Maximum number of byte enable bits

Maximum number of bits in a uvm_reg_cvr_t coverage model set.

Maximum data width in bits

Define blocking mask onehot assignment = ‘b100

The macro wraps the function b_transport() Execute a blocking transaction.

Defines Not-Yet-Implemented TLM functions

Define Non blocking backward mask onehot assignment = ‘b010

Define Non blocking Forward mask onehot assignment = ‘b001

Implementation of the backward path.

The macro wraps the forward path call function nb_transport_fw()

Defines Not-Yet-Implemented TLM tasks

Unpack a dynamic array without having to also specify the bit size of its elements.

Unpack into a dynamic array of integrals.

Unpack an enumeration value, which requires its type be specified.

Unpack enum of type TYPE into VAR.

Unpack an integral variable without having to also specify the bit size.

Unpack into an integral variable.

Unpack a queue without having to also specify the bit size of its elements.

Unpack into a queue of integrals.

Unpack a variable of type real.

Unpack a static array without having to also specify the bit size of its elements.

Unpack a static (fixed) array of integrals.

Unpack a string variable.

Calls uvm_report_warning with a verbosity of UVM_NONE.

This macro pair operates identically to `uvm_info_begin/`uvm_info_end with exception that the message severity is UVM_WARNING and has no verbosity threshold.

To ease the process of migrating code to UVM 1.2, the old (incorrect) behavior remain available.

The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog.

Many of the backwards compatibility concerns caused when transitioning from UVM version 1.1 to 1.2 can be addressed with a reasonably simple search-and-replace in user code.

In UVM 1.3, the UVM object factory will have the corrected behavior ONLY.

bit abstract = 1

This bit provides a filtering mechanism for fields.

bit abstract

This bit provides a filtering mechanism for fields.

bit abstract = 1

This bit provides a filtering mechanism for fields.

string abstractions[$]

If set, check the HDL paths for the specified design abstractions.

pure virtual function void accept(
    STRUCTURE s,
    VISITOR v,
    uvm_structure_proxy#(STRUCTURE) p,
    bit invoke_begin_end = 1

)

Calling this function will traverse through s (and every subnode of s).

function void accept_tr (
uvm_transaction tr,
time accept_time = 0

)

This function marks the acceptance of a transaction, tr, by this component.

function void accept_tr (
time accept_time = 0

)

Calling accept_tr indicates that the transaction item has been received by a consumer component.

The accessor functions let you set and get each of the members of the generic payload.

uvm_reg_adapter adapter

The adapter used to convey the parameters of a bus operation in terms of a canonical uvm_reg_bus_op datum.

uvm_reg_adapter adapter

Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

static function void add(
    T obj,
    uvm_callback cb,
    uvm_apprepend ordering = UVM_APPEND

)

Registers the given callback object, cb, with the given obj handle.

function void add (
uvm_component comp

)

Add a single component to the set of components to be monitored.

function void add(
    uvm_phase phase,
    uvm_phase with_phase = null,
    uvm_phase after_phase = null,
    uvm_phase before_phase = null

)

Build up a schedule structure inserting phase by phase, specifying linkage

virtual function void add (
KEY key,
T item

)

Adds the given (key, item) pair to the pool.

static function void add(
uvm_reg rg

)

Add this callback to the specified register and its contained fields.

static function void add(
uvm_reg rg

)

Add this callback to the specified register and its contained fields.

static function void add_by_name(
    string name,
    uvm_callback cb,
    uvm_component root,
    uvm_apprepend ordering = UVM_APPEND

)

Registers the given callback object, cb, with one or more uvm_components.

virtual function void add_callback (
uvm_event_callback#(T) cb,
bit append = 1

)

Registers a callback object, cb, with this event.

virtual protected function void add_coverage(
uvm_reg_cvr_t models

)

Specify that additional coverage models are available.

virtual protected function void add_coverage(
uvm_reg_cvr_t models

)

Specify that additional coverage models are available.

virtual protected function void add_coverage(
uvm_reg_cvr_t models

)

Specify that additional coverage models are available.

function void add_hdl_path (
uvm_hdl_path_slice slices[],
string kind = "RTL"

)

Add an HDL path

function void add_hdl_path (
uvm_hdl_path_slice slices[],
string kind = "RTL"

)

Add an HDL path

function void add_hdl_path (
string path,
string kind = "RTL"

)

Add an HDL path

function void add_hdl_path (
string path,
string kind = "RTL"

)

Add an HDL path

function void add_hdl_path_slice(
    string name,
    int offset,
    int size,
    bit first = 0,
    string kind = "RTL"

)

Add the specified HDL slice to the HDL path for the specified design abstraction.

function void add_hdl_path_slice(
    string name,
    int offset,
    int size,
    bit first = 0,
    string kind = "RTL"

)

Append the specified HDL slice to the HDL path of the register instance for the specified design abstraction.

protected function void add_int(
    string name,
    uvm_bitstream_t value,
    int size,
    uvm_radix_enum radix,
    uvm_action action = (UVM_LOG|UVM_RM_RECORD)

)

Add an integral type of the name name and value value to the message.

virtual function void add_int(
    string name,
    uvm_bitstream_t value,
    int size,
    uvm_radix_enum radix,
    uvm_action action = (UVM_LOG|UVM_RM_RECORD)

)

This method adds an integral type of the name name and value value to the message.

virtual function void add_int(
    string name,
    uvm_bitstream_t value,
    int size,
    uvm_radix_enum radix,
    uvm_action action = (UVM_LOG|UVM_RM_RECORD)

)

This method adds an integral type of the name name and value value to the container.

virtual function void add_mem (
    uvm_mem mem,
    uvm_reg_addr_t offset,
    string rights = "RW",
    bit unmapped = 0,
    uvm_reg_frontdoor frontdoor = null

)

Add a memory

protected function void add_object(
    string name,
    uvm_object obj,
    uvm_action action = (UVM_LOG|UVM_RM_RECORD)

)

Adds a uvm_object of the name name and reference obj to the message.

virtual function void add_object(
    string name,
    uvm_object obj,
    uvm_action action = (UVM_LOG|UVM_RM_RECORD)

)

This method adds a uvm_object of the name name and reference obj to the message.

virtual function void add_object(
    string name,
    uvm_object obj,
    uvm_action action = (UVM_LOG|UVM_RM_RECORD)

)

This method adds a uvm_object of the name name and reference obj to the message.

function void add_path(
    string path,
    int unsigned offset = -1,
    int unsigned size = -1

)

Append the specified path to the path concatenation, for the specified number of bits at the specified offset.

virtual function void add_reg (
    uvm_reg rg,
    uvm_reg_addr_t offset,
    string rights = "RW",
    bit unmapped = 0,
    uvm_reg_frontdoor frontdoor = null

)

Add a register

function void add_sequence(
uvm_object_wrapper seq_type

)

Registers the provided sequence type with this sequence library instance.

virtual function void add_sequences(
uvm_object_wrapper seq_types[$]

)

Registers the provided sequence types with this sequence library instance.

function void add_slice(
uvm_hdl_path_slice slice

)

Append the specified slice literal to the path concatenation

protected function void add_string(
    string name,
    string value,
    uvm_action action = (UVM_LOG|UVM_RM_RECORD)

)

Adds a string of the name name and value value to the message.

virtual function void add_string(
    string name,
    string value,
    uvm_action action = (UVM_LOG|UVM_RM_RECORD)

)

This method adds a string of the name name and value value to the message.

virtual function void add_string(
    string name,
    string value,
    uvm_action action = (UVM_LOG|UVM_RM_RECORD)

)

This method adds a string of the name name and value value to the message.

virtual function void add_submap (
uvm_reg_map child_map,
uvm_reg_addr_t offset

)

Add an address map

static function void add_typewide_sequence(
uvm_object_wrapper seq_type

)

Registers the provided sequence type with this sequence library type.

static function void add_typewide_sequences(
uvm_object_wrapper seq_types[$]

)

Registers the provided sequence types with this sequence library type.

static function void add_uvm_phases(
uvm_phase schedule

)

Appends to the given schedule the built-in UVM phases.

uvm_reg_addr_t addr

The bus address.

virtual protected function string adjust_name (
string id,
byte scope_separator = "."

)

Prints a field’s name, or id, which is the full instance name.

The export to which a data stream of type AFTER is sent via a connected analysis port.

The export to which the other stream of data is written.

A common function of testbenches is to compare streams of transactions for equivalence.

virtual task all_dropped (
    uvm_objection objection,
    uvm_object source_obj,
    string description,
    int count

)

The all_droppped callback is called when all objections have been dropped by this component and all its descendants.

virtual task all_dropped (
    uvm_object obj,
    uvm_object source_obj,
    string description,
    int count

)

Objection callback that is called when a drop_objection has reached obj, and the total count for obj goes to zero.

virtual task all_dropped (
    uvm_objection objection,
    uvm_object obj,
    uvm_object source_obj,
    string description,
    int count

)

Objection all_dropped callback function.

Memory allocation mode

virtual function uvm_mem_region allocate(
    longint unsigned n,
    uvm_mem_mam mam,
    uvm_mem_mam_policy alloc = null

)

Randomly implement, resize or relocate a virtual register array

The analysis interface is used to perform non-blocking broadcasts of transactions to connected components.

This section defines the port, export, and imp classes used for transaction analysis.

This export provides access to the write method, which derived subscribers must implement.

The analysis_export provides the write method to all connected analysis ports and parent exports:

virtual function void apply_config_settings (
bit verbose = 0

)

Searches for all config settings matching this component’s instance path.

To find out what is happening as the simulation proceeds, an audit trail of each read and write is kept.

virtual task b_transport(
T t,
uvm_tlm_time delay

)

Execute a blocking transaction.

References to the values within uvm_sequence_state_enum and uvm_sequencer_arb_mode must now be prefixed with UVM_.

static function uvm_reg_map backdoor()

Return the backdoor pseudo-map singleton

virtual protected task backdoor_read(
uvm_reg_item rw

)

User-define backdoor read access

virtual task backdoor_read(
uvm_reg_item rw

)

User-define backdoor read access

virtual function uvm_status_e backdoor_read_func(
uvm_reg_item rw

)

User-defined backdoor read access

virtual function uvm_status_e backdoor_read_func(
uvm_reg_item rw

)

User-defined backdoor read access

virtual task backdoor_watch()

User-defined DUT register change monitor

virtual task backdoor_write(
uvm_reg_item rw

)

User-defined backdoor read access

virtual task backdoor_write(
uvm_reg_item rw

)

User-defined backdoor read access

Care must be taken when switching from set_config_object and get_config_object to uvm_config_object, as the clone functionality of the old API no longer exists.

The undocumented uvm_pkg::factory variable has been removed, as it was unsafe during static initialization, and incompatible with the uvm_coreservice_t class.

Specifies the sequence type to extend from.

string bd_kind

If path is UVM_BACKDOOR, this member specifies the abstraction kind for the backdoor access, e.g.

The export to which a data stream of type BEFORE is sent via a connected analysis port.

The export to which one stream of data is written.

function integer begin_child_tr (
    uvm_transaction tr,
    integer parent_handle = 0,
    string stream_name = "main",
    string label = "",
    string desc = "",
    time begin_time = 0

)

This function marks the start of a child transaction, tr, by this component.

function integer begin_child_tr (
time begin_time = 0,
integer parent_handle = 0

)

This function indicates that the transaction has been started as a child of a parent transaction given by parent_handle.

int begin_elements = 5

Defines the number of elements at the head of a list to print.

uvm_event#(
uvm_object

) begin_event

A uvm_event#(uvm_object) that is triggered when this transaction’s actual execution on the bus begins, typically as a result of a driver calling uvm_component::begin_tr.

Beginning of request phase

Beginning of response phase

function integer begin_tr (
    uvm_transaction tr,
    string stream_name = "main",
    string label = "",
    string desc = "",
    time begin_time = 0,
    integer parent_handle = 0

)

This function marks the start of a transaction, tr, by this component.

function integer begin_tr (
time begin_time = 0

)

This function indicates that the transaction has been started and is not the child of another transaction.

virtual function void begin_v()

This method will be invoked by the visitor before the first NODE is visited

The bidirectional interfaces consist of blocking, non-blocking, and combined blocking and non-blocking variants of the transport, master, and slave interfaces.

bit big_endian = 1

This bit determines the order that integral data is packed (using pack_field, pack_field_int, pack_time, or pack_real) and how the data is unpacked from the pack array (using unpack_field, unpack_field_int, unpack_time, or unpack_real).

string bin_radix = "'b"

This string should be prepended to the value of an integral type when a radix of UVM_BIN is used for the radix of the integral object.

This section defines classes that test individual bits of the registers defined in a register model.

The blocking_put_port is used to send the generated stimulus to the rest of the testbench.

virtual task body()

Execute the Memory Access sequence.

virtual task body()

Performs the walking-ones algorithm on each map of the memory specified in mem.

virtual task body()

Executes the mem walk sequence, one block at a time.

virtual task body()

Executes the Register Access sequence.

virtual task body()

Executes the Register Bit Bash sequence.

virtual task body()

Executes the Hardware Reset sequence.

virtual task body()

Executes any or all the built-in register and memory sequences.

virtual task body()

Executes the Shared Register and Memory sequence

virtual task body()

Continually gets a register transaction from the configured upstream sequencer, reg_seqr, and executes the corresponding bus transaction via do_reg_item.

virtual task body()

This is the user-defined task where the main sequence code resides.

protected function uvm_reg_cvr_t build_coverage(
uvm_reg_cvr_t models

)

Check if all of the specified coverage model must be built.

protected function uvm_reg_cvr_t build_coverage(
uvm_reg_cvr_t models

)

Check if all of the specified coverage models must be built.

protected function uvm_reg_cvr_t build_coverage(
uvm_reg_cvr_t models

)

Check if all of the specified coverage model must be built.

virtual function void build_phase(
uvm_phase phase

)

The uvm_build_phase phase implementation method.

virtual task burst_read(
    output uvm_status_e status,
    input uvm_reg_addr_t offset,
    ref uvm_reg_data_t value[],
    input uvm_path_e path = UVM_DEFAULT_PATH,
    input uvm_reg_map map = null,
    input uvm_sequence_base parent = null,
    input int prior = -1,
    input uvm_object extension = null,
    input string fname = "",
    input int lineno = 0

)

Read values from memory locations

task burst_read(
    output uvm_status_e status,
    input uvm_reg_addr_t offset,
    output uvm_reg_data_t value[],
    input uvm_path_e path = UVM_DEFAULT_PATH,
    input uvm_reg_map map = null,
    input uvm_sequence_base parent = null,
    input int prior = -1,
    input uvm_object extension = null,
    input string fname = "",
    input int lineno = 0

)

Read from a set of memory location in the region.

virtual task burst_write(
    output uvm_status_e status,
    input uvm_reg_addr_t offset,
    input uvm_reg_data_t value[],
    input uvm_path_e path = UVM_DEFAULT_PATH,
    input uvm_reg_map map = null,
    input uvm_sequence_base parent = null,
    input int prior = -1,
    input uvm_object extension = null,
    input string fname = "",
    input int lineno = 0

)

Write the specified values in memory locations

task burst_write(
    output uvm_status_e status,
    input uvm_reg_addr_t offset,
    input uvm_reg_data_t value[],
    input uvm_path_e path = UVM_DEFAULT_PATH,
    input uvm_reg_map map = null,
    input uvm_sequence_base parent = null,
    input int prior = -1,
    input uvm_object extension = null,
    input string fname = "",
    input int lineno = 0

)

Write to a set of memory location in the region.

uvm_analysis_imp #(
BUSTYPE,
uvm_reg_predictor #(BUSTYPE)

) bus_in

Observed bus transactions of type BUSTYPE are received from this port and processed.

pure virtual function void bus2reg(
uvm_sequence_item bus_item,
ref uvm_reg_bus_op rw

)

Extensions of this class must implement this method to copy members of the given bus-specific bus_item to corresponding members of the provided bus_rw instance.

virtual function void bus2reg(
uvm_sequence_item bus_item,
ref uvm_reg_bus_op rw

)

Converts a uvm_tlm_gp item to a uvm_reg_bus_op.

uvm_reg_byte_en_t byte_en

Enables for the byte lanes on the bus.