| Register Defines | |
| Macros | |
| `UVM_REG_ADDR_WIDTH | Maximum address width in bits |
| `UVM_REG_DATA_WIDTH | Maximum data width in bits |
| `UVM_REG_BYTENABLE_WIDTH | Maximum number of byte enable bits |
| `UVM_REG_CVR_WIDTH | Maximum number of bits in a uvm_reg_cvr_t coverage model set. |
Maximum address width in bits
Default value is 64. Used to define the uvm_reg_addr_t type.
Maximum data width in bits
Default value is 64. Used to define the uvm_reg_data_t type.
Maximum number of byte enable bits
Default value is one per byte in `UVM_REG_DATA_WIDTH. Used to define the uvm_reg_byte_en_t type.
Maximum number of bits in a uvm_reg_cvr_t coverage model set.
Default value is 32.