Global Declarations for the Register Layer

This section defines globally available types, enums, and utility classes.

Summary
Global Declarations for the Register Layer
This section defines globally available types, enums, and utility classes.
Types
uvm_reg_data_t2-state data value with `UVM_REG_DATA_WIDTH bits
uvm_reg_data_logic_t4-state data value with `UVM_REG_DATA_WIDTH bits
uvm_reg_addr_t2-state address value with `UVM_REG_ADDR_WIDTH bits
uvm_reg_addr_logic_t4-state address value with `UVM_REG_ADDR_WIDTH bits
uvm_reg_byte_en_t2-state byte_enable value with `UVM_REG_BYTENABLE_WIDTH bits
uvm_reg_cvr_tCoverage model value set with `UVM_REG_CVR_WIDTH bits.
uvm_hdl_path_sliceSlice of an HDL path
Enumerations
uvm_status_eReturn status for register operations
uvm_path_ePath used for register operation
uvm_check_eRead-only or read-and-check
uvm_endianness_eSpecifies byte ordering
uvm_elem_kind_eType of element being read or written
uvm_access_eType of operation begin performed
uvm_hier_eWhether to provide the requested information from a hierarchical context.
uvm_predict_eHow the mirror is to be updated
uvm_coverage_model_eCoverage models available or desired.
uvm_reg_mem_tests_eSelect which pre-defined test sequence to execute.
Utility Classes

Types

uvm_reg_data_t

2-state data value with `UVM_REG_DATA_WIDTH bits

uvm_reg_data_logic_t

4-state data value with `UVM_REG_DATA_WIDTH bits

uvm_reg_addr_t

2-state address value with `UVM_REG_ADDR_WIDTH bits

uvm_reg_addr_logic_t

4-state address value with `UVM_REG_ADDR_WIDTH bits

uvm_reg_byte_en_t

2-state byte_enable value with `UVM_REG_BYTENABLE_WIDTH bits

uvm_reg_cvr_t

Coverage model value set with `UVM_REG_CVR_WIDTH bits.

Symbolic values for individual coverage models are defined by the uvm_coverage_model_e type.

The following bits in the set are assigned as follows

0-7UVM pre-defined coverage models
8-15Coverage models defined by EDA vendors, implemented in a register model generator.
16-23User-defined coverage models
24..Reserved

uvm_hdl_path_slice

Slice of an HDL path

Struct that specifies the HDL variable that corresponds to all or a portion of a register.

pathPath to the HDL variable.
offsetOffset of the LSB in the register that this variable implements
sizeNumber of bits (toward the MSB) that this variable implements

If the HDL variable implements all of the register, offset and size are specified as -1.  For example:

r1.add_hdl_path('{ '{"r1", -1, -1} });

Enumerations

uvm_status_e

Return status for register operations

UVM_IS_OKOperation completed successfully
UVM_NOT_OKOperation completed with error
UVM_HAS_XOperation completed successfully bit had unknown bits.

uvm_path_e

Path used for register operation

UVM_FRONTDOORUse the front door
UVM_BACKDOORUse the back door
UVM_PREDICTOperation derived from observations by a bus monitor via the uvm_reg_predictor class.
UVM_DEFAULT_PATHOperation specified by the context

uvm_check_e

Read-only or read-and-check

UVM_NO_CHECKRead only
UVM_CHECKRead and check

uvm_endianness_e

Specifies byte ordering

UVM_NO_ENDIANByte ordering not applicable
UVM_LITTLE_ENDIANLeast-significant bytes first in consecutive addresses
UVM_BIG_ENDIANMost-significant bytes first in consecutive addresses
UVM_LITTLE_FIFOLeast-significant bytes first at the same address
UVM_BIG_FIFOMost-significant bytes first at the same address

uvm_elem_kind_e

Type of element being read or written

UVM_REGRegister
UVM_FIELDField
UVM_MEMMemory location

uvm_access_e

Type of operation begin performed

UVM_READRead operation
UVM_WRITEWrite operation

uvm_hier_e

Whether to provide the requested information from a hierarchical context.

UVM_NO_HIERProvide info from the local context
UVM_HIERProvide info based on the hierarchical context

uvm_predict_e

How the mirror is to be updated

UVM_PREDICT_DIRECTPredicted value is as-is
UVM_PREDICT_READPredict based on the specified value having been read
UVM_PREDICT_WRITEPredict based on the specified value having been written

uvm_coverage_model_e

Coverage models available or desired.  Multiple models may be specified by bitwise OR’ing individual model identifiers.

UVM_NO_COVERAGENone
UVM_CVR_REG_BITSIndividual register bits
UVM_CVR_ADDR_MAPIndividual register and memory addresses
UVM_CVR_FIELD_VALSField values
UVM_CVR_ALLAll coverage models

uvm_reg_mem_tests_e

Select which pre-defined test sequence to execute.

Multiple test sequences may be selected by bitwise OR’ing their respective symbolic values.

UVM_DO_REG_HW_RESETRun uvm_reg_hw_reset_seq
UVM_DO_REG_BIT_BASHRun uvm_reg_bit_bash_seq
UVM_DO_REG_ACCESSRun uvm_reg_access_seq
UVM_DO_MEM_ACCESSRun uvm_mem_access_seq
UVM_DO_SHARED_ACCESSRun uvm_reg_mem_shared_access_seq
UVM_DO_MEM_WALKRun uvm_mem_walk_seq
UVM_DO_ALL_REG_MEM_TESTSRun all of the above

Test sequences, when selected, are executed in the order in which they are specified above.

Utility Classes

uvm_hdl_path_concat

Concatenation of HDL variables

A dArray of uvm_hdl_path_slice specifying a concatenation of HDL variables that implement a register in the HDL.

Slices must be specified in most-to-least significant order.  Slices must not overlap.  Gaps may exist in the concatenation if portions of the registers are not implemented.

For example, the following register

       1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
Bits:  5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
      +-+---+-------------+---+-------+
      |A|xxx|      B      |xxx|   C   |
      +-+---+-------------+---+-------+

If the register is implemented using a single HDL variable, The array should specify a single slice with its offset and size specified as -1.  For example:

concat.set('{ '{"r1", -1, -1} });
Summary
uvm_hdl_path_concat
Concatenation of HDL variables
Class Declaration
class uvm_hdl_path_concat
Variables
slicesArray of individual slices, stored in most-to-least significant order
Methods
setInitialize the concatenation using an array literal
add_sliceAppend the specified slice literal to the path concatenation
add_pathAppend the specified path to the path concatenation, for the specified number of bits at the specified offset.

Variables

slices

uvm_hdl_path_slice slices[]

Array of individual slices, stored in most-to-least significant order

Methods

set

function void set(
    uvm_hdl_path_slice  t[]
)

Initialize the concatenation using an array literal

add_slice

function void add_slice(
    uvm_hdl_path_slice  slice
)

Append the specified slice literal to the path concatenation

add_path

function void add_path(
    string  path,   
    int  unsigned  offset  =  -1,
    int  unsigned  size  =  -1
)

Append the specified path to the path concatenation, for the specified number of bits at the specified offset.

Maximum data width in bits
Maximum address width in bits
Maximum number of byte enable bits
Maximum number of bits in a uvm_reg_cvr_t coverage model set.
Coverage models available or desired.
class uvm_reg_predictor #(
    type  BUSTYPE  =  int
) extends uvm_component
Updates the register model mirror based on observed bus transactions
class uvm_reg_hw_reset_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Test the hard reset values of registers
class uvm_reg_bit_bash_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the implementation of all registers in a block by executing the uvm_reg_single_bit_bash_seq sequence on it.
class uvm_reg_access_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the accessibility of all registers in a block by executing the uvm_reg_single_access_seq sequence on every register within it.
class uvm_mem_access_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the accessibility of all memories in a block by executing the uvm_mem_single_access_seq sequence on every memory within it.
class uvm_reg_mem_shared_access_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the accessibility of all shared registers and memories in a block by executing the uvm_reg_shared_access_seq and uvm_mem_shared_access_seq sequence respectively on every register and memory within it.
class uvm_mem_walk_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verifies the all memories in a block by executing the uvm_mem_single_walk_seq sequence on every memory within it.
class uvm_hdl_path_concat
Concatenation of HDL variables
uvm_hdl_path_slice slices[]
Array of individual slices, stored in most-to-least significant order
function void set(
    uvm_hdl_path_slice  t[]
)
Initialize the concatenation using an array literal
function void add_slice(
    uvm_hdl_path_slice  slice
)
Append the specified slice literal to the path concatenation
function void add_path(
    string  path,   
    int  unsigned  offset  =  -1,
    int  unsigned  size  =  -1
)
Append the specified path to the path concatenation, for the specified number of bits at the specified offset.
Slice of an HDL path