- New School Thinking for Fast and Efficient Verification Using EZ-VIP - Online | April 28th
With the complexity and interoperability needs of today's systems the use of standard interfaces such as PCIe and MIPI is a must. Verification of IP to implement these interfaces for re-use within a wide variety of systems can be time consuming and hard to get right. Users of IP are often faced with issues of integration and getting caught in the complex details of the IP implementation when their real goal is to verify design specific and system functionality. Verification IP is available to solve these issues, but too often comes with a high integration effort and a steep learning curve of its own that users must overcome before they can become truly productive.
This webinar will cover the use of UVM based verification IP for protocols such as PCI Express and MIPI CSI and DSI.
- Trends in FPGA and ASIC/IC Functional Verification - Online | May 6th
This web seminar presents the most recent FPGA Verification Trends findings from the 2014 Wilson Research Group and Mentor Graphics industry study on functional verification.
- New School Coverage Closure - Online | May 28th
Management of complex SoC development projects to the point of successful coverage closure has become a very challenging job. Design and verification engineers spend enormous amounts of time reviewing coverage holes. This presentation discusses a new school formal verification method which automates the job of focusing coverage closure efforts on the items which actually need to be hit and the results achieved on a large SoC design in the entertainment and signal processing domain.
- Verification Academy at DAC - San Francisco | June 8th - 11th
Visit the Verification Academy booth #2408 on the DAC exhibit floor where Mentor will be digging deeper into the challenges of IC Design and Verification with presentations and lively conversation.
- Trends in FPGA and ASIC/IC Functional Verification - Online | June 16th
This web seminar presents the most recent ASIC/IC Verification Trends findings from the 2014 Wilson Research Group and Mentor Graphics industry study on functional verification.
- New School Connectivity Checking - Online | June 30th
One of the primary goals of SoC-level verification is to ensure that all top-level connections have been made correctly. However, this is no easy task. Today's SoC designs contain large numbers of design IP blocks, interconnected through multiple on-chip bus fabrics and point-to-point connections, which can result in interconnect signals that number in the thousands. This session discusses the use of a new school formal verification method which can be easily applied to solve the problem of connectivity checking with detailed case studies of how this formal app was used to automatically verify connectivity and accelerate the debug process.