March 2014:
- DVCon 2014 - March 3rd - 6th | San Jose, CA
Mentor Graphics delivers the most comprehensive and unified advanced verification portfolio available: including Questa® for high performance simulation and debug, verification management and coverage closure, low-power verification with UPF, CDC, Formal Verification, accelerated functional coverage, processor-based hardware verification and Veloce® for high-performance system verification.
- Injecting Automation into Verification - FPGA Market Trends - March 18th | 8:00 AM - 9:00 AM US/Pacific
This webinar is a manager's introduction to trends in the FPGA market and provide a business perspective on how companies are crossing the FGPA design verification barrier. Learn the common tools, techniques and learning aids that make an effective FPGA verification process. We will discuss the business and technical merits of common techniques and processes that your team can start deploying now. This series has three main concepts, coverage metrics, assertions for debug, and verification throughput. Each of the three concepts can be adopted incrementally or entirely and are offered as separate technical webinars.
- Injecting Automation into Verification - Code Coverage - March 20th | 8:00 AM - 9:00 AM US/Pacific
Code Coverage is a method used to determine the effectiveness of the testbench for a piece of HDL code, which it does by measuring and indicating what percentage of the design was exercised by this testbench. The concept originally came from the software world where this is used in almost every software development organisation in their verification cycles. Despite the similarity of HDL code to software written in languages such as C, it is not so extensively used in HDL code verification.
- Injecting Automation into Verification - Assertions - March 25th | 8:00 AM - 9:00 AM US/Pacific
Assertions have proven value in identifying bugs where and when they occur. This is one dimension of improving debug throughput. This webinar will show how you can leverage Assertions, including the pre-defined, pre-tested OVL libraries. Automation is an essential component in adoption of technology; we will highlight our Assertion Manager. The Assertion Manager will help you identify and create pre-configured checkers so that you can improve your debug productivity associated with Assertions, as the monitoring of the Assertions is done fully automatically by the simulator. This further reduces the load of the engineer during verification and regression.
- Mentor Forum - March 25th | Tel Aviv, Israel
Mentor Forum Israel brings together engineers and managers coming from all electronics companies in Israel. We've packed the day full of exciting activities focused on the latest in cutting-edge design. Choose from numerous presentations, including keynotes and breakout tracks on topics addressing the following domains: IC design and test, physical verification, SoC verification, functional verification and PCB systems.
- Injecting Automation into Verification - Improved Throughput - March 27th | 8:00 AM - 9:00 AM US/Pacific
This webinar will focus on the highest value tools and techniques for improving test stimulus, debug effectiveness and simulation throughput. One of the most common verification process improvement opportunities is being able to more easily create test cases, including leveraging standard bus interfaces like PCIe for stimulating your system. We will also describe common techniques for improving simulation performance. If you are able to stimulate your design with simulation more effectively you will find that debug productivity in simulation is vastly superior to debug time in an hardware lab. We will show common and recent improvements in simulation debug throughput. We also highlight additional pre-built verification automation components for verification process throughput.
Archived:
Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. Harry Foster discusses the results from the 2012 Wilson Research Group Functional Verification Study, and provides some insight into its findings.
Watch and Learn:
- Latest industry trends in design.
- Latest industry trends in verification.
- An analytical interpretation of the study results.