Upcoming Web Seminar - Verification IP - May 24th
Overview
Today's designs rely heavily on a growing variety of complex industry standard interfaces that must be verified to ensure IP interoperability and system behavior. Mentor's verification IP (VIP) improves quality and reduces schedule times by building Mentor’s protocol and methodology expertise into a library of reusable components that support many industry standard interfaces. This frees up engineering resources from having to spend time developing BFMs, verification components, or VIP themselves, enabling them to focus on the unique and high-value aspects of their design.
What You Will Learn
- Rapidly generate verification IP components most common protocols use in UVM or OVM testbench environment
- Use build in sequence items quickly create transaction on your protocol bus
- Use built in transaction streams to view transactions in the wave window, raising abstraction level of debug
- Identify critical protocol features and use VIP sequences and coverage to verify testing of these features
- Rapidly generate memory models and quickly integrate them into any testbench using Mentor’s memory configurator software
- Verify your memory controllers with assertions, coverage, and transaction level debug
- Easily switch between primary and second source memory models using Mentor’s unique on-the-fly reconfiguration
Learn more and register.
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Recent Seminar Recording
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Verification Academy Live: Portable Stimulus Seminar
Overview:
This seminar will tell you everything you need to know about the upcoming Accellera Portable Test and Stimulus Standard, which was developed specifically to address this verification challenge. Experts from Mentor who are leading participants of the Accellera Portable Stimulus Working Group will provide a detailed look at how the new standard allows you to specify your verification intent at an abstract level to make you more productive in creating scenarios. You'll also see how Portable Stimulus can be used on real-life examples to generate coverage-driven tests in multiple output formats, including UVM and C.
Featured Sessions:
- Why a Portable Stimulus Standard?
- Portable Stimulus Standard (PSS) Uncovered
- PSS Usage Examples: Low Power & SoC Memory Subsystem Verification
Session recordings now available to view or download.
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Recent Web Seminar Recordings
Are you an ASIC/IC/FPGA Verification Engineer or Manager interested in DO-254 and Advanced Verification?
Web Seminar Title:
An Introduction to DO-254 and Advanced Verification
Overview:
The consequences of a bug in airborne electronic hardware (AEH) can potentially be catastrophic. DO-254 was established to ensure that the potential for hardware bugs is addressed in a consistent and verifiable manner. It defines a set of guidelines that should be followed to ensure that your AEH design safely performs its intended function in its specified environment(s). Even if your design is not AEH, you'll still find the "best practice" guidelines helpful.
DO-254 describes the objectives of a verification process to allow the development of systems that meet your design assurance goals. This web seminar will explain the critical aspects of a DO-254-compliant process and show how many advanced verification techniques and tools may be applied to satisfy these objectives.
What You Will Learn:
- What is DO-254?
- What do I have to do to satisfy DO-254?
- How can I take advantage of new verification technologies under DO-254?
- What does Mentor offer to help me implement a leading-edge DO-254 verification process?
Now available to view or download.
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Are you an ASIC/IC/FPGA Verification Engineer or Manager interested in SoC Verification Flows?
Web Seminar Title:
Breaking the Speed Limits on SoC Verification with the Questa® Flow
Overview:
In this web seminar, you will learn best practice in verification flows in the industry today, and how to implement the optimal flow to speed your SoC design verification cycle.
What You Will Learn:
- Block-, Subsystem-, and SoC-level verification flows in common use in the industry today
- How best practice in design of the verification flow leads to improved productivity
- How Mentor's Questa® Simulator is providing highest performance across the flow
Now available to view or download.
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Are you an ASIC/IC, FPGA Verification Engineer or Manager interested in CDC Verification?
Web Seminar:
What Is CDC Protocol Verification, and Why You Absolutely Need It To Prevent Bugs in Your Silicon
Overview:
Multi-clock designs are subject to metastability, which causes mismatches between traditional simulation and silicon reality. Adding synchronization structures is not sufficient for preventing CDC bugs in silicon. This web seminar explains the importance of CDC protocols for correct synchronizer operation. Through a set of detailed examples, we show how CDC protocol failure in clock domain crossings will lead to functional problems and silicon failure. We discuss the pros and cons of various approaches to verifying CDC protocols and we show how Questa® CDC automatically generates protocol assertions for a complete dynamic CDC verification methodology that includes simulation and formal analysis.
What You Will Learn:
- How metastability can lead to functional issues in silicon.
- Why synchronization structures alone are not sufficient to prevent CDC functional issues.
- How Questa® CDC enables you to eliminate CDC protocol issues caused by metastability.
Now available to view or download.
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Are you an ASIC/IC, FPGA Verification Engineer or Manager interested in Portable Stimulus?
Web Seminar Title:
Automating Reusable Retargetable Scenario-level Tests with Portable Stimulus
Overview:
In this web seminar, you will learn how graph-based portable stimulus raises the abstraction level of test specification and execution, and enables tests to be retargeted across environments and execution platforms.
- How graph-based portable stimulus enables automation of scenario-level tests
- How portable stimulus enables easily retargeting tests to different environments
- How Mentor's Questa® inFact enables users to achieve these results today
Now available to view or download.
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Are you an ASIC/IC, FPGA Design/Verification Engineer, Project Lead or Manager interested in the latest design and verification trends?
Please join Verification Academy Subject Matter Expert, Harry Foster for an upcoming web seminar.
Web Seminar Title:
The 2016 Wilson Research Group ASIC/IC and FPGA Functional Verification Study
What You Will Learn:
Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster highlights the key findings from the 2016 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
- Latest industry ASIC/IC and FPGA trends in design
- Latest industry ASIC/IC and FPGA trends in verification
- An analytical interpretation of the study results
Now available to view or download.
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Are you a Verification Engineer or Manager interested in advanced verification techniques?
Web Seminar Title:
Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy
What You Will Learn:
In this web seminar, we will share five steps your team can take to adopt widely used technologies and standards such as SV/UVM, UCIS and UPF, and achieve first pass success:
- Adopt a verification methodology and improve your stimulus in one hour
- Get started and get finished with easy Coverage measurements and reports
- Organize and manage your self-checking parallel regression test suite
- Use Verification IP to tackle the added complexity of todays' plethora of interfaces
- Adopt low power design and add UPF to your flow the easy way
Now available to view or download.
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View the entire Functional Verification Calendar.