- Optimizing Simulation Runtime Performance with Questa - Fremont, CA | August 19th
Achieving optimum verification efficiency often requires the analysis of RTL simulation runtime to look for bottlenecks and potential improvements. This session will provide an introduction to the Performance Profiler feature on the Questa Simulator and show examples of how it can be used to detect and root cause typical performance bottlenecks seen in RTL simulation using Questa.
- New School Regression Control - Online | August 27th
Getting the very best from your verification resources requires a regression system that understands the verification process and is tightly integrated with Workload Management and Distributed Resource Management software. Both requirements depend on visibility into available software and hardware resources, and by combining their strengths, users can massively improve productivity by reducing unnecessary verification cycles.
This session will show how adding control and visibility to these systems, and then better integrating them, will help your organization get the very best from every verification dollar. It will also highlight how separating control from the configuration data in a regression system improves maintenance and user productivity. Major features can be coded into the system itself instead of added as a series of scripts with multiple calling levels, which often lead to a debug nightmare.
- New Low Power Verification Techniques - Online | September 10th
IEEE 1801 UPF enables specification of power intent early in the design flow, to drive both verification and implementation processes. But power management decisions must be made incrementally throughout the flow, often by different people at each stage. Power intent specifications need to be structured in a manner that reflects these stages, to organize the information effectively, to ensure clear communication among IP providers, designers, and implementers, and to maximize reuse of power intent. This session highlights a "new school" low power methodology termed "successive refinement" that uses the strength of UPF in just such a structured approach. It will explain what kinds of power intent information should be captured at each stage, which features of UPF are involved in doing so, and how this structured approach benefits both IP providers and IP users.
View the entire Functional Verification Calendar.