DVCon 2016 | February 29th - March 3rd | San Jose, CA
Mentor Graphics delivers the most comprehensive Enterprise Verification Platform (EVP), which combines Questa for high performance simulation, verification management and coverage closure, low-power verification with UPF, CDC, Formal Verification, accelerated functional coverage, and processor-based hardware verification, Veloce OS3 global emulation technology, the Visualizer debug environment, to deliver performance and productivity improvements ranging from 400X to 10,000X, and Catapult and PowerPro providing complete solutions for High Level Synthesis/Verification and Low Power Analysis and Optimization.
Don’t miss these exciting Mentor Graphics events at this year’s conference!
Register for DVCon 2016.
The UVM standard class library provides everything you need to build modular reusable verification environments for everything from individual IP blocks to subsystems and systems. Unfortunately, with a wide array of tools at your disposal in UVM, many users can get caught up in one aspect of their testbench development and lose sight of the overall goal, which is to be as productive as possible.
We are excited to bring you a comprehensive agenda of the very latest topics to help existing UVM users and those that are new or interested in UVM. Please join hosts Harry Foster and Tom Fitzpatrick for this Verification Academy Live seminar that will include sessions discussing:
- Easing adoption of UVM
- UVM Debug
- Portable Stimulus
- UVM Acceleration.
View the entire Functional Verification Calendar.