FPGA vendors continue to innovate creating new ways for FPGA users to more efficiently design into today's increasingly complex FPGAs. This has created a widening gap between design abstraction and verification of these FPGAs in which traditional verification approaches come up short. As a result, the balance is shifting as more FPGA users want and need to adopt modern verification practices in order to be competitive. Unfortunately, they don't always know where to start, or find that the cost/risk is too great to embark on. In this session you will learn about trends in the FPGA industry that are pushing the need for advanced verification, understand how other FPGA users in the industry are adapting to this and see how taking a new look at your verification methodologies and tools can help you build higher quality, on-time products enabling you to be more competitive in today’s evolving FPGA market.
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The UVM standard class library provides everything you need to build modular reusable verification environments for everything from individual IP blocks to subsystems and systems. Unfortunately, with a wide array of tools at your disposal in UVM, many users can get caught up in one aspect of their testbench development and lose sight of the overall goal, which is to be as productive as possible.
View the entire Functional Verification Calendar.