Upcoming Verification Events | Verification Academy

The Verification Academy Booth #617 has 3 full days of advanced functional verification open theater sessions:

Monday, June 3rd:

Portable Stimulus: Is It Revolution or Evolution?
First Pass Success Depends on Holistic Planning that Includes Formal
How Do You Know When to Stop Looking for CDC Issues?
Mentor Safe IC – End-to-end Functional Safety Flow
Debugging Your Design in a Heterogeneous Environment
RISC-V Core & SoC Compliance, Verification, Customization
Stay Ahead of the Curve: Questa Verification IP and Portable Stimulus Maximize Your UVM Productivity

Tuesday, June 4th:

SoC Verification Problems From Early Software To System Implementation
Scaling Acceleration Productivity Beyond HW
Selecting the Most Productive SoC Design Verification Techniques
IP Development Methodology on HYCON
Have Your Cake and Eat it Too: Make the Most of your UVM Environment for Coverage Closure AND Bug Hunting with PSS Infused Apps for SystemVerilog
Mixed-Signal Challenges for Digitally Assisted nm-CMOS High Speed SerDes Targeted for 5G and Automotive Applications
Plan Driven and Requirements Driven Verification

Wednesday, June 5th:

An Emulation Strategy for Artificial Intelligence and Machine Learning Devices
What's Missing and What Should Be Next for SystemVerilog
DFT Enablement for AI Devices
Methodology to Debug Real Number Model Boundary Scenarios using Symphony & Questa Visualizer Debug Environment
Chips&Media: Deep Learning Accelerator Using HLS
“River Fishing”: Using Coverage for Formal Bug Hunting
UVM and Portable Stimulus: A Match Made in Heaven