Web Seminar: CDC Protocol Verification - December 8th | 8:00 - 9:00 AM US/Pacific
Multi-clock designs are subject to metastability, which causes mismatches between traditional simulation and silicon reality. Adding synchronization structures is not sufficient for preventing CDC bugs in silicon. This webinar explains the importance of CDC protocols for correct synchronizer operation. Through a set of detailed examples, we show how CDC protocol failure in clock domain crossings will lead to functional problems and silicon failure. We discuss the pros and cons of various approaches to verifying CDC protocols and we show how Questa CDC automatically generates protocol assertions for a complete dynamic CDC verification methodology that includes simulation and formal analysis.
What You Will Learn:
- How metastability can lead to functional issues in silicon
- Why synchronization structures alone are not sufficient to prevent CDC functional issues
- How Questa CDC enables you to eliminate CDC protocol issues caused by metastability
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FPGA vendors continue to innovate creating new ways for FPGA users to more efficiently design into today's increasingly complex FPGAs. This has created a widening gap between design abstraction and verification of these FPGAs in which traditional verification approaches come up short. As a result, the balance is shifting as more FPGA users want and need to adopt modern verification practices in order to be competitive. Unfortunately, they don't always know where to start, or find that the cost/risk is too great to embark on. In this session you will learn about trends in the FPGA industry that are pushing the need for advanced verification, understand how other FPGA users in the industry are adapting to this and see how taking a new look at your verification methodologies and tools can help you build higher quality, on-time products enabling you to be more competitive in today's evolving FPGA market.
View the entire Functional Verification Calendar.