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Upcoming Verification Events

April 2014:

  • IESF 2014: Military and Aerospace - April 22nd | Dallas, TX - April 24th | Everett, WA - May 1st | Long Beach, CA

    IESF is the global destination for electrical/electronic engineers, managers, and executives in the military and aerospace sectors. For the past 14 years, IESF has been at the forefront of bringing the most brilliant minds together to discuss industry trends, best practices, and product solutions—covering a variety of EE system design disciplines.

    More information and register.

May 2014:

  • Questa Verification IP Workshop - May 6th | Fremont, CA

    This workshop provides an in-depth look at Questa Verification IP (QVIP). QVIP provides a comprehensive test suite, a test plan derived from the protocol specification, assertion-based checks to ensure protocol compliance, and transaction-level debug. QVIP promotes utilization of reusable test bench building blocks, is in compliance with industry standards and protocols, and is ready to deploy in verification environments employing advanced methodologies such as UVM.

    More information and register.

  • Step-up Your Verification Efficiency - May 7th | Kista, Sweden

    In this seminar we will provide perspectives into the market forces that are driving FPGA development environments, show you a common and practical example of an improved verification process and show you the resources to deploy. You can effectively break the FPGA design verification barrier.

    More information and register.


  • Injecting Automation into Verification - FPGA Market Trends - Webinar

    This archived webinar is a manager's introduction to trends in the FPGA market and provide a business perspective on how companies are crossing the FPGA design verification barrier. Learn the common tools, techniques and learning aids that make an effective FPGA verification process. We will discuss the business and technical merits of common techniques and processes that your team can start deploying now. This series has three main concepts, coverage metrics, assertions for debug, and verification throughput.

    More information and register.

  • Injecting Automation into Verification – Code Coverage - Webinar

    This archived webinar provides an introduction to the use of code coverage in today's HDL design and verification flows. Without code coverage the designer will find it hard (or impossible) to know if all aspects of the RTL code have been exercised by the testbench. Code Coverage is built into the simulator and it will tell the designer which areas have been exercised and, much more importantly, which have not. Without the use of Code Coverage it is highly likely that key parts of the functionality of a design have not been fully verified which leaves the possibility of bugs slipping through the scope of the regression tests.

    More information and register.

  • Injecting Automation into Verification - Assertions - Webinar

    What we will show in this archived webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way in which the Assertion Manager will create pre-configured checkers as well as how to debug the results of an assertion failing. As the monitoring of the Assertions is done fully automatically by the simulator this further reduces the load of the engineer during verification and regression.

    More information and register.

  • Injecting Automation into Verification – Improved Throughput - Webinar

    This archived webinar will focus on the highest value tools and techniques for improving test stimulus, debug effectiveness and simulation throughput. One of the most common verification process improvement opportunities is being able to more easily create test cases, including leveraging standard bus interfaces like PCIe for stimulating your system. We will also describe common techniques for improving simulation performance. If you are able to stimulate your design with simulation more effectively you will find that debug productivity in simulation is vastly superior to debug time in an hardware lab. We will show common and recent improvements in simulation debug throughput. We also highlight additional pre-built verification automation components for verification process throughput.

    More information and register.

  • 2012 Functional Verification Study

Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. Harry Foster discusses the results from the 2012 Wilson Research Group Functional Verification Study, and provides some insight into its findings.

Watch and Learn:

  • Latest industry trends in design.
  • Latest industry trends in verification.
  • An analytical interpretation of the study results.

View the entire Functional Verification Calendar.

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