Design verification methodologies are in an endless race to catch up with exploding verification needs. As soon as the verification industry standardizes on a methodology, a new set of requirements emerges. While methodologies like coverage-driven test ranking and sophisticated checkers can help focus the verification results on the most high-value data points, a real live person must still sift through all of the output and navigate the failure analysis–bug identification–fix–validate cycle. The debug challenge is big and is only growing.
Indeed, based on semi-annual customer surveys debug is now exceeding 39% of an engineer's time, which is more than any other single verification task. Clearly, improving debug productivity for an enterprise flow from block to system pre-silicon verification, virtual prototyping, emulation, as well as post-silicon validation is critical to stay on schedule and simultaneously meet quality goals. Join us for this comprehensive seminar to learn the very latest verification techniques.
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The October meet up of the NMI FPGA Network will share experiences of how design tools and methodologies impact the schedule, solve difficult problems, affect quality, optimize architecture, bridge hardware and software communities. It will provide a stage for end users (the good workmen) and solutions and service providers (also good workmen) to praise what works well so all can benefit from the knowledge.
Staying Competitive by Evolving Your FPGA Verification Methodologies
FPGA vendors continue to create new ways for FPGA users to efficiently design into complex FPGAs. This has created a widening gap between design abstraction and verification on which traditional verification approaches come up short. As a result, more FPGA users want and need to adopt modern verification practices to be competitive. Unfortunately, they don't always know where to start or find the cost/risk too great. In this session you will learn about themes in the industry that are pushing the need for advanced verification, understand how FPGA users are adapting and see how a new look at verification methodologies helps build higher quality, on-time products.
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Metastability from the intermixing of multiple clock signals is not modeled by simulation. Unless you leverage exhaustive, automated Clock Domain Crossing (CDC) analyses to identify and correct problem areas, you will inevitably suffer unpredictable behavior when the chip samples come back from the fab. These problems are only compounded when your reset signaling network gets caught up in the mix as well. Hence, the focus of this free, half-day Verification Academy seminar is on how you can get the most out of automated, formal-based CDC analysis – including the latest techniques and real-world customer case studies. Register today!
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FPGA vendors continue to innovate creating new ways for FPGA users to more efficiently design into today's increasingly complex FPGAs. This has created a widening gap between design abstraction and verification of these FPGAs in which traditional verification approaches come up short. As a result, the balance is shifting as more FPGA users want and need to adopt modern verification practices in order to be competitive. Unfortunately, they don't always know where to start, or find that the cost/risk is too great to embark on. In this session you will learn about trends in the FPGA industry that are pushing the need for advanced verification, understand how other FPGA users in the industry are adapting to this and see how taking a new look at your verification methodologies and tools can help you build higher quality, on-time products enabling you to be more competitive in today's evolving FPGA market.
View the entire Functional Verification Calendar.