Where can I find timing diagram for write and read in axi4 protocol?

UVM
1

I have to write a test which include axi4 protocol.
Where can I find timing diagram for write and read in axi4 protocol?

2

In reply to saritr:

AXI specification document has all you need. If you have any particular doubts in those waveforms or how to implement?

3

In reply to mayurkubavat:

I have to write a transaction class for the axi bus, and a driver (just for testing read and write). Im not sure what are the properties that I must include in the transaction, and effect on the driver.

4

In reply to saritr:

You can start with a small functionality. For e.g.,

  • Consider only write channel, take address, control signals and array for data in transaction class.
  • Constraint address with address word boundary, 4KB boundary and data array size with Length etc.

Receive this transaction and write onto write interface in driver. Additionally, you’ll be observing AWREADY and WREADY signals coming from slave component.

Similar way, increase functionality for write channels, add functionality for Read Channel. Gradual addition of code will work with small pre-planning. You may like to consider effect of Reset signal and how it affects all signals.

5

In reply to mayurkubavat:

In reply to saritr:
You can start with a small functionality. For e.g.,

  • Consider only write channel, take address, control signals and array for data in transaction class.
  • Constraint address with address word boundary, 4KB boundary and data array size with Length etc.
    Receive this transaction and write onto write interface in driver. Additionally, you’ll be observing AWREADY and WREADY signals coming from slave component.
    Similar way, increase functionality for write channels, add functionality for Read Channel. Gradual addition of code will work with small pre-planning. You may like to consider effect of Reset signal and how it affects all signals.

But what about the other properties/functionalites. Is it ok not send them to the interface through the driver? Shouldn’t I put some const in them?

6

In reply to mayurkubavat:

When I implement the interface of the axi bus, should I include all the signals?

ACLK
ARESETn
AWID
AWADDR
AWLEN
AWSIZE
AWBURST
AWLOCK
AWCACHE
AWPROT
AWQOS
AWREGION
AWUSER
AWVALID
AWREADY
WID
WDATA
WSTRB
WLAST
WUSER
WVALID
WREADY
BID
BRESP
BUSER
BVALID
BREADY
ARID
ARADDR
ARLEN
ARSIZE
ARBURST
ARLOCK
ARCACHE
ARPROT
ARQOS
ARREGION
ARUSER
ARVALID
ARREADY
RID
RDATA
RRESP
RLAST
RUSER
RVALID
RREADY

7

In reply to saritr:

Yes. To implement total functionality you need to include all the signals in IF. But, initially its ok to ignore values on other signals as you are implementing selected functionality.

One way to start implementation is, to select related signals and implement code for that only(For e.g. Only Write Address Channel). You can have few constraint initially, and start adding constraints as you mark each functionality.

To track progress, you should consider developing verification plan, to list number of functionality you are going to implement.

Also, as write and read channels are independent, you can have separate Drivers or UVCs for them.

8

In reply to mayurkubavat:

What is UVC?
If I ignore values won’t I get errors?

9

In reply to mayurkubavat:

What is the motivation for separate Drivers to the write and read channel?