In reply to mayurkubavat:
When I implement the interface of the axi bus, should I include all the signals?
ACLK
ARESETn
AWID
AWADDR
AWLEN
AWSIZE
AWBURST
AWLOCK
AWCACHE
AWPROT
AWQOS
AWREGION
AWUSER
AWVALID
AWREADY
WID
WDATA
WSTRB
WLAST
WUSER
WVALID
WREADY
BID
BRESP
BUSER
BVALID
BREADY
ARID
ARADDR
ARLEN
ARSIZE
ARBURST
ARLOCK
ARCACHE
ARPROT
ARQOS
ARREGION
ARUSER
ARVALID
ARREADY
RID
RDATA
RRESP
RLAST
RUSER
RVALID
RREADY