Well , all this depends on the packet granularity that your golden reference model(SystemC) works on.
* Higher the granularity -> higher the probability of mismatch -> Higher simulation speed
* Lower the granularity -> result may closer to match -> Simulation speed goes down{increasing the sampling events}
So, here decision is made on the basis of choice.
As let me discuss a case,
1. a protocol implementing the data transfer on data bus running at clock1.
2. another bus program bus running at clock2.
Now if data transfer on going , on the same time program bus access the status registers, hardware always gives different output from untimed model SystemC.
So here some ways are:
a. Tune the sequences as per the requirement , i.e, on model and hardware sync boundaries.
b. Build a wrapper on the top of SystemC Module and mimic the behavior of time {need not to model time just put the timing in terms of mathematical equations} and process the same.
Both the above will pollute.
But anyways , a friend of mine gives me suggestion to create cycle accurate model , as the rtl integrated env is already slow , so cycle accurate need not be exploiting the speed of simulation issue which is already slow.
Fortunately , Ruchir Bharti STMicroelectronics, may soon be publishing a paper on this. All the above suggestion are derived from his discussion. I would try posting the paper soon after the NASUG conference {when published}.
Cheers,
Karandeep
