What is Null point access

UVM
1

Hi,

Can you describe about the Null point access error in UVM?

Thanks,
prawin

2

That error will come when either a component or a object is not created.

3

In reply to saurabh_3:

1 function void connect_phase(uvm_phase phase);
2 if(is_active == UVM_ACTIVE)begin
3 driver.seq_item_port.connect(sequencer.seq_item_export);
4 end

I’m getting null point access error in line 3.

4

In reply to Prawin kumar:

In reply to saurabh_3:
1 function void connect_phase(uvm_phase phase);
2 if(is_active == UVM_ACTIVE)begin
3 driver.seq_item_port.connect(sequencer.seq_item_export);
4 end
I’m getting null point access error in line 3.

Check whether you created driver and sequencer in the agent. Also check for the name of handle of both driver and sequencer.

5

In reply to saurabh_3:

yes,i created driver and sequencer in the agent only,

still getting that fatal error.

function void build_phase(uvm_phase phase);
super.build();
if(is_active == UVM_ACTIVE)begin
sequencer = ac_lpc_sequencer::type_id::create(“sequencer”,this);
driver = ac_lpc_driver::type_id::create(“driver”,this);
end
else begin
monitor = ac_lpc_monitor::type_id::create(“monitor”,this);
end
endfunction

function void connect_phase(uvm_phase phase);

if(is_active == UVM_ACTIVE)begin
(164) driver.seq_item_port1.connect(sequencer.seq_item_export);
end

Fatal Error: RUNTIME_0029 testbench.sv (164): Null pointer access.

6

In reply to Prawin kumar:

Your driver has a seq_item_port, but not a seq_item_port1.
Please be careful sending your requests.

7

In reply to chr_sue:

OK,but i’m declare analysis port of driver as a seq_item_port1 only,

that’s what “driver.seq_item_port1.connect(sequencer.seq_item_export);”

is it Wrong?

8

In reply to Prawin kumar:

The uvm_driver has a built-in seq_item_port which is intended to be connected to the sequence item_export of the sequencer. You can create an analysis_port in your driver. Analysis ports are intended for sending out data for further processing like coverage and scoreboards.
I recommedn to watch the UVM videos from the Verification Academy.

9

In reply to chr_sue:

ok chr_sue,

but i have doubt regarding of analysis ports,

example - uvm_analysis_port(sequence_item)seq_item_port

can we write seq_item_port by any other name ,because of its just port name yes?

10

In reply to Prawin kumar:

From where did you get this decaration:
uvm_analysis_port(sequence_item)seq_item_port

seq_item_port is a name only. For all references you do it is your choice.
But seq_item_port is reserved name, because it is used in the UVM base class library.

11

In reply to chr_sue:

Hi,

That declaration iam getting from one of uvm_book,
Is The declaration correct or not?

Thanks,
Prawin

12

In reply to Prawin kumar:

Could you please point me to this declaration?

13

In reply to chr_sue:

Hi,

Analysis Ports

Thanks

14

In reply to Prawin kumar:

But it does not say, this is the connection between sequencer and driver. An analysis port is used for data needed for analysing, like functional coverage or scoreboard connections.
It is not applicable for the interface between the sequencer and driver.

15

Driver and Sequencer can use a pair of built-in pull ports to communicate transactions. Driver calls seq_item_port.get_next_item() to have sequencer produce transactions and pass to driver.

//in uvm_driver:
uvm_seq_item_pull_port #(REQ, RSP) seq_item_port;
//in uvm_sequencer:
uvm_seq_item_pull_export #(REQ, RSP) seq_item_export;
//in agent:
driver.seq_item_port.connect(sequencer.seq_item_export);

uvm_analysis_port is used to broadcast the transactions to a list of uvm_analysis_export ports. When you declare uvm_analysis_port in your driver, it means driver wants to broadcast the transactions to its peer exports, is this your purpose? Probably not.

Usually, uvm_analysis_port is used in monitor so that it can broadcast the collected transactions to uvm_analysis_export ports in coverage or scoreboard etc. components for further analysis.

16

In reply to Lina.Lin:

Hi Lina,

Can we write ‘seq_item’(class name extended from uvm_sequence_item) instead of (REQ,RSP) in port declarations.
Because of REQ,RSP related to transactions of seq_item i.e uvm_sequence_item.

Thanks,
Prawin

17

In reply to Prawin kumar:

REQ, RSP are the type parameters of uvm_driver #(REQ,RSP) and uvm_sequencer #(REQ,RSP) components and its default type is uvm_sequence_item (please check the uvm_driver.svh code below). When you derive your own driver and sequencer from uvm_driver and uvm_sequencer, you can pass your sequence item type such as “seq_item” as you mentioned to replace the default one.

For example:
class my_driver extends uvm_driver #(seq_item);

This will automatically replace all REQ, RSP type as “seq_item” type for seq_item_port, seq_item_prod_if, rsp_port, req and rsp declarations of uvm_driver. You can use these built-in data and ports directly, don’t need to re-declare as they are already in uvm_driver for use.



typedef class uvm_sequence_item;

//------------------------------------------------------------------------------
//
// CLASS: uvm_driver #(REQ,RSP)
//
// The base class for drivers that initiate requests for new transactions via
// a uvm_seq_item_pull_port. The ports are typically connected to the exports of
// an appropriate sequencer component.
//
// This driver operates in pull mode. Its ports are typically connected to the
// corresponding exports in a pull sequencer as follows:
//
//|    driver.seq_item_port.connect(sequencer.seq_item_export);
//|    driver.rsp_port.connect(sequencer.rsp_export);
//
// The ~rsp_port~ needs connecting only if the driver will use it to write
// responses to the analysis export in the sequencer.
//
//------------------------------------------------------------------------------

class uvm_driver #(type REQ=uvm_sequence_item,
                   type RSP=REQ[/b]) extends uvm_component;


  // Port: seq_item_port
  //
  // Derived driver classes should use this port to request items from the
  // sequencer. They may also use it to send responses back.

  uvm_seq_item_pull_port #(REQ, RSP) seq_item_port; 

  uvm_seq_item_pull_port #(REQ, RSP) seq_item_prod_if; // alias 

  // Port: rsp_port
  //
  // This port provides an alternate way of sending responses back to the
  // originating sequencer. Which port to use depends on which export the
  // sequencer provides for connection.

  uvm_analysis_port #(RSP) rsp_port;

  REQ req;
  RSP rsp;

  // Function: new
  //
  // Creates and initializes an instance of this class using the normal
  // constructor arguments for <uvm_component>: ~name~ is the name of the
  // instance, and ~parent~ is the handle to the hierarchical parent, if any.

  function new (string name, uvm_component parent);
    super.new(name, parent);
    seq_item_port    = new("seq_item_port", this);
    rsp_port         = new("rsp_port", this);
    seq_item_prod_if = seq_item_port;
  endfunction // new

  const static string type_name = "uvm_driver #(REQ,RSP)";

  virtual function string get_type_name ();
    return type_name;
  endfunction

endclass
18

In reply to Lina.Lin:

Hi,

Now am get a clarity on REQ,RSP.

Thank you for valuable information Lina.

Thanks,
Prawin