In reply to chr_sue:
ok chr_sue,
but i have doubt regarding of analysis ports,
example - uvm_analysis_port(sequence_item)seq_item_port
can we write seq_item_port by any other name ,because of its just port name yes?
In reply to chr_sue:
ok chr_sue,
but i have doubt regarding of analysis ports,
example - uvm_analysis_port(sequence_item)seq_item_port
can we write seq_item_port by any other name ,because of its just port name yes?