Virtual interface for internal signals

UVM
, ,
1

I need to have access to some signals that are not inputs or outputs of the DUT.
I need to monitor reads and writes to a data cache. How do I set up a virtual
interface for internal signals?

2

In reply to dave41266:

You can use the SV bind-construct to observe/stimulate any internal signals. This allows you also to use a SY interface to connect to.

3

In reply to dave41266:

See Updated Example Code from DVCon Paper: The Missing Link: The Testbench to DUT Connection | Verification Academy

4

In reply to chr_sue:

Hi…so you mean we can connect our DUT to interface using bind construct in top module. For example, if my interface name is “intf” & DUT module name is “dut”, then can i use bind construct in top module like this as shown below ?
module top();
…

intf intf(clk);//interface instantiation
dut DUT(.clk(intf.clk),.wr(intf.wr)…);//dut instantiation
bind dut intf dpm(.clk(clk),.wr(wr)…);//binding dut with interface
…

endmodule

Thanks in advance