Virtual interface and DUT interface compilation error

UVM
,
1

Dear All,

I’m trying to figure out the compilation error when I interface the virtual interface and DUT.

-testbench.sv

`include "uvm_macros.svh"
import uvm_pkg::*;

class my_driver extends uvm_driver;                             
`uvm_component_utils(my_driver)                                 
  
virtual my_interface vintf;  
  
function new(string name = "", uvm_component parent);
    super.new(name, parent);
endfunction
  
function void build_phase(uvm_phase phase);
  
if(! uvm_config_db#(virtual my_interface)::get(this, "", "vintf_my_interface", vintf))      
`uvm_error("", "!!uvm_config_db get fail!!!!");                                             
endfunction                                                                                 
                                                                                            
task run_phase(uvm_phase phase);                                                            
	vintf.a = 6;
	vintf.b = 7;
	$display(" %d, %d, %d",vintf.a, vintf.b, vintf.c);
endtask                                                                                     
                                                                                            
endclass                                                                                    
                                                                                            
                                                                                            
                                                                                            
class my_env extends uvm_env;
  `uvm_component_utils(my_env)

my_driver p_driver;

function new (string name ="", uvm_component parent);
super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);
p_driver = my_driver::type_id::create("p_driver", this);
endfunction

endclass


class my_test extends uvm_test;

`uvm_component_utils(my_test)

my_env p_env;

function new(string name, uvm_component parent);
super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);
p_env = my_env::type_id::create("p_env",this);
endfunction

task run_phase(uvm_phase phase);
  endtask

endclass





module top();
import uvm_pkg::*;

//virtual my_interface intf;

initial begin
//uvm_config_db#(virtual my_interface)::get(null, "*", "vintf_my_interface", intf);
run_test("my_driver");

end


endmodule

-design.sv

// Code your design here
interface my_interface(

  input  logic [31:0] a,
  input  logic[31:0]  b,
  output logic[31:0]  c
);
endinterface


module sub(
  input  reg [31:0] a   ,
  input  reg [31:0] b   ,
  output wire [31:0] c
); 
    import uvm_pkg::*;
  assign c = a + b;

my_interface vintf_my_interface(
.a(sub.a),
.b(sub.b),
.c(sub.c));

initial begin
uvm_config_db#(virtual my_interface)::set(null, "*", "vintf_my_interface",vintf_my_interface);

end

endmodule

When I ran the above code, I’ve got the below error message

	vintf.a = 6;
	    |
ncelab: *E,WANOTL (./testbench.sv,20|5): A net is not a legal lvalue in this context [9.3.1(IEEE)].
	vintf.b = 7;
	    |
ncelab: *E,WANOTL (./testbench.sv,21|5): A net is not a legal lvalue in this context [9.3.1(IEEE)].
irun: *E,ELBERR: Error during elaboration (status 1), exiting.
Exit code expected: 0, received: 1

I can’t understand why vintf is to be a net type?

2

In reply to UVM_LOVE:

You have declared the signals a and b in interface file as inputs.
Since they are inputs you can’t drive values to them.

BTW you have to use non-blocking assignment to drive the output signals of the interface.

3

In reply to Sushimohan:

// Code your design here

interface my_interface(

  output  logic [31:0] a,
  output  logic[31:0]  b,
  input logic[31:0]  c
);
endinterface


module sub(
  input  reg [31:0] a   ,
  input  reg [31:0] b   ,
  output wire [31:0] c
); 
    import uvm_pkg::*;
  assign c = a + b;

my_interface vintf_my_interface(
.a(sub.a),
.b(sub.b),
.c(sub.c));

initial begin
uvm_config_db#(virtual my_interface)::set(null, "*", "vintf_my_interface",vintf_my_interface);

end

endmodule

[code tags added by editor]

This changes works fine

4

In reply to Sushimohan:

Thanks! It’s work! Great.