Virtual interface and DUT interface compilation error

UVM
,
3

In reply to Sushimohan:

// Code your design here

interface my_interface(

  output  logic [31:0] a,
  output  logic[31:0]  b,
  input logic[31:0]  c
);
endinterface


module sub(
  input  reg [31:0] a   ,
  input  reg [31:0] b   ,
  output wire [31:0] c
); 
    import uvm_pkg::*;
  assign c = a + b;

my_interface vintf_my_interface(
.a(sub.a),
.b(sub.b),
.c(sub.c));

initial begin
uvm_config_db#(virtual my_interface)::set(null, "*", "vintf_my_interface",vintf_my_interface);

end

endmodule

[code tags added by editor]

This changes works fine