VHDL Slicing in RAL Backdoor Paths - Possible?

UVM
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1

Hi,

I’m going through the registers on my project and defining backdoor paths, and I’ve run into a particular issue I can’t seem to solve. I have my register block configured similar to this:


reg_model_h.configure(.hdl_path("top.dut"));

For most registers, using add_hdl_path_slice() works fine. However, I get errors when trying to do this:


reg_model.example_reg.add_hdl_path_slice("registers.example_reg(10 downto 9)", .offset(9), .size(2));

My understanding is the cause of this failing is that Questa (what I’m using) requires brackets to evaluate correctly:


"{top.dut.registers.example_reg(10 downto 9)}"

As far as I can tell, I can’t add brackets around the full path. Adding them around the slice doesn’t work as the block path is still prepended to it, and that doesn’t evaluate correctly. I’ve considered setting it directly after adding the slice, but I can only get the path, there’s no direct set method as far as I can see. Are my assumptions correct, and is this task possible?

2

Hi - I found the solution - I’d assumed VHDL code meant I needed to use (M downto N) syntax, but the truth is you can just use SystemVerilog [M:N] syntax. You don’t need curly brackets, my fix was with the following method:


reg_model.example_reg.add_hdl_path_slice("registers.example_reg[10:9]", .offset(9), .size(2));

My guess is this is because the backdoor access method is in SystemVerilog and maybe the way it evaluates is different to how Questa evaluates paths.