Hello,
I am performing a rd/wr check of a register but its mirrored value is modified in zero sim time when a read is immediately followed by a write to the same register. Any thoughts and suggestions on this issue are greatly appreciated.
This causes trouble when I perform coverage collection (and perhaps other analysis) when the read completes. I actually trigger an event in the register callback post predict routine and monitor that event in coverage collectors and other analysis components. The coverage collection or other analysis may see the value received from the read or the value being attempted during the write. This is because the write function immediately performs an unconditional call of the set() function. I have seen others mention this in the links below:
http://cluelogic.com/2013/02/uvm-tutorial-for-candy-lovers-register-access-methods/#comment-12331
Is this simply a limitation of UVM? I know I could use the read transaction generated by the agent’s monitor to trigger my analysis. However I prefer the event technique because I do not need to decode the address in the transaction from the monitor.
Example sequence code:
my_reg_h.write(status, '1);
my_reg_h.mirror(status, .check(UVM_CHECK), .path(UVM_FRONTDOOR));
my_reg_h.write(status, '0);
my_reg_h.mirror(status, .check(UVM_CHECK), .path(UVM_FRONTDOOR));
In the example above the analysis components may see a mirrored value all 1s or 0s when triggered by an event at the end of the read.
Regards,
Josh