UVM_REG Backdoor writes

UVM
1

Hello,

I am trying the following FD-WR → FD_RD → BD_RD → BD_WR → BD_RD

In this case, I can see the backdoor read working properly but for some reason the backdoor write doesn’t seem to work. If it was an issue with hdl path, the BD read shouldn’t have worked.
I was wondering what is a good way to debug BD writes and if there is anything obvious that I should be looking for in my regmodel.

Thanks
Subramaniam

2

In reply to ssubramaniam:

Could you please a Little bit more your problem. Do you get an error message or a wrong value. Which commands you are using for backdoor (peek/poke or read/write)?

3

In reply to chr_sue:

I am using read/write() for backdoor.

I don’t see any error messages. From my logs:

Here I am doing FD write → BD read → BD write → BD read (all via write() and read()):
UVM_INFO @ 15660: reporter [RegMem] backdoor_read from register_test_top.abc_top.o_dummy
UVM_INFO @ 15660: reporter [RegMem] returned backdoor value 0xdeadbe11
UVM_INFO @ 15660: reporter [RegModel] Read register via DPI backdoor: regmodel.abc_top.DUMMY=deadbe11

UVM_INFO @ 15660: reporter [RegMem] backdoor_write to register_test_top.abc_top.o_dummy
UVM_INFO @ 15660: reporter [RegModel] Wrote register via DPI backdoor: regmodel.abc_top.DUMMY=0xbaddc0de
UVM_INFO @ 15660: [backdoor_write] Writing baddc0de to register: DUMMY

UVM_INFO @ 15660: reporter [RegMem] backdoor_read from register_test_top.abc_top.o_dummy
UVM_INFO @ 15660: reporter [RegMem] returned backdoor value 0xdeadbe11
UVM_INFO @ 15660: reporter [RegModel] Read register via DPI backdoor: regmodel.abc_top.DUMMY=deadbe11

4

In reply to ssubramaniam:
I would try some experiments using the UVM DPI routines directly. Try writing and reading a simple variable, then your register. That will tell you if there is something wrong with your register configuration, or with the DPI access.

5

In reply to dave_59:

Thanks Dave for the suggestion.

I tried adding a register to the DUT and tried the following:

uvm_hdl_deposit
uvm_hdl_read
uvm_hdl_force
uvm_hdl_read

uvm_hdl_read reads the value the reg was initialized with. But somehow deposit and force doesn’t seem to work. But checking their statuses, they all return 1 which means they succeeded.

If deposit() isn’t working, what should be my next step here?

Thanks
Subramaniam

6

In reply to ssubramaniam:
You may need to look at the user manual of your tool about preserving visibility and optimization. It possible you have read visibility, but not write visibility. I guessing the UVM DPI/VPI code is not smart enough to know the difference.

7

In reply to ssubramaniam:

Did you check the UVM_STATUS after the backdoor write?
Instead of the write you could also use the poke command.

8

In reply to chr_sue:

Thanks for your suggestion.

Actually it turned out to be a tool related issue and am working with them.