In reply to dave_59:
Thanks Dave for the suggestion.
I tried adding a register to the DUT and tried the following:
uvm_hdl_deposit
uvm_hdl_read
uvm_hdl_force
uvm_hdl_read
uvm_hdl_read reads the value the reg was initialized with. But somehow deposit and force doesn’t seem to work. But checking their statuses, they all return 1 which means they succeeded.
If deposit() isn’t working, what should be my next step here?
Thanks
Subramaniam