UVM_RAL::Linking Mirror models for a register accessible through two addresses on the same physical interface

UVM
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We have a specific type of register in our design, which have two addresses to access the same physical register. When accessed through the first address, the behavior expected is W1S (Write one to set) and when accessed through the second address, the expected behavior is W1C (write one to clear). I have below questions:

  1. Is anyone aware of a single RAL entity that behaves as per above specifications. ie. has two addresses, single mirror model, and exhibits different access policies when accessed through each address.

  2. The nearest I could do is implement two RAL entities, one at first address and another at second address. They would have W1S and W1C access policies respectively. Is there a way I could link the two mirror models of the registers? So whether I write through the first address or the second address, both the mirror models are to be updated.

Any input is highly appreciated.

Thanks