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  • uvm_hdl_read() works only with STD_LOGIC_VECTOR. (for INTEGER or ENUM (e.g. FSM), only 0 is returned, or a random INTEGER value.

uvm_hdl_read() works only with STD_LOGIC_VECTOR. (for INTEGER or ENUM (e.g. FSM), only 0 is returned, or a random INTEGER value.

UVM 6740
uvm_hdl_read STD_LOGIC... 1
vlad_velea
vlad_velea
Full Access
3 posts
March 27, 2023 at 6:54 am

Hi

Using uvm_hdl_read()it only seems to work for STD_LOGIC_VECTOR. If the signal is an INTEGER or ENUM (e.g. FSM), only 0 is retured, or an implausible value with an integer signal...

Is this something wrong or does it just work only with STD_LOGIC_VECTOR?

Thanks,
Vlad

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chr_sue
chr_sue
Full Access
3890 posts
March 28, 2023 at 1:57 am

In reply to vlad_velea:

uvm_hdl_read() is a UVM utility based on SystemVerilog. std_logic_vector is a VHDL construct. There is no interoperability defined between both languages.

vlad_velea
vlad_velea
Full Access
3 posts
March 28, 2023 at 2:18 am

Perfectly true. This is the svh agent:

hdl_status = uvm_hdl_read("hdl_top.DUT.abc_fsm_inst.state_r", hdl_data);
...
hdl_status = uvm_hdl_read("hdl_top.DUT.abc__fsm_inst.state_stdv_s", hdl_data);
....
hdl_status = uvm_hdl_read("hdl_top.DUT.abc_fsm_inst.shift_cnt_r", hdl_data);
..
hdl_status = uvm_hdl_read("hdl_top.DUT.abc_fsm_inst.shift_cnt_stdv_s", hdl_data);

vhdl signals & conversion

SIGNAL sck_cnt_r :INTEGER RANGE 0 TO (2**cfg_sclk_div_cnt_i'LENGTH) := 1;
SIGNAL sck_cnt_stdv_s :STD_LOGIC_VECTOR(cfg_sclk_div_cnt_i'LENGTH-1 DOWNTO 0);
SIGNAL shift_cnt_r :INTEGER RANGE 0 TO ADC_DATA_BW_C := 0;
SIGNAL shift_cnt_stdv_s:STD_LOGIC_VECTOR(INTEGER(CEIL(LOG2(REAL(ADC_DATA_BW_C))))-1 DOWNTO 0);

state_stdv_s <= state2stdv(state_r);
shift_cnt_stdv_s <= STD_LOGIC_VECTOR(TO_UNSIGNED(shift_cnt_r,shift_cnt_stdv_s'LENGTH));
sck_cnt_stdv_s <= STD_LOGIC_VECTOR(TO_UNSIGNED(sck_cnt_r,sck_cnt_stdv_s'LENGTH));

Questa output

# UVM_INFO D:/...[READ HDL PATH shift_cnt]] shift_cnt_r: 0x00000000 - Status: 1 - shift_cnt_stdv_r: 0x00000000 - Status: 1
# UVM_INFO D:/... [READ HDL PATH state]] state_r: 0x00000000 - Status: 1 - state_stdv_s: 0x00000000 - Status: 1

Please advise.

chr_sue
chr_sue
Full Access
3890 posts
March 28, 2023 at 10:59 am

In reply to vlad_velea:

I'd use a bind contruct to connect to the VHDL world. The bind connects a SV module and you can use uvm_hdl_read() without any limitation.

vlad_velea
vlad_velea
Full Access
3 posts
March 28, 2023 at 11:09 pm

In reply to chr_sue:

The instantiation of the VHDL DUT is tool generated inside SV i.e.:

DUT(
.sys_clk_i(uvm_abc_bus.sys_clk),
.reset_n_i(reset_n),
.avs_address_i(avs_address),
.avs_write_i(avs_write),
.avs_writedata_i(avs_writedata),
.avs_read_i(avs_read),
.avs_readdata_o(avs_readdata),
.....
);

Where exactly to use bind?

Thanks,
Vlad

chr_sue
chr_sue
Full Access
3890 posts
March 28, 2023 at 11:33 pm

In reply to vlad_velea:

You are observing DUT internal signals, Right. You can connect to any internal signal using the SV bind construct.

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