I have rewritten some test infrastructures to be more reusable. Everything is looking good-- but at the end of the test-- the objections lower-- the drain time expires and finish gets called: but I am not longer getting the “-- UVM Report Summary —” at the end of the tests.
We also made the move to UVM 1.2.
I made sure to called the super functions in all my areas. I never manually instantiate the uvm_reporter…
Any ideas?
In reply to wpiman:
Your simulation does not come to a normal end. You should see a message like this.
reporter [TEST_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase
Debug the execution of your sequences.
In reply to chr_sue:
I don’t see the message…
reporter [TEST_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase
But if I put this line in my base test class…
function void extract_phase(uvm_phase phase);
super.extract_phase(phase);
`uvm_info(get_type_name(), $psprintf(“extract phase”), UVM_NONE)
endfunction
I see that I enter the extract phase in my log at the expected time…
My drivers and monitors run in the run_phase… I am starting my sequence in the main_phase. Pretty typical.
Shouldn’t I expect to see that message when I get to the later function phases? Is there perhaps a switch or modelsim ini line I changed?
This image show that the extract functions are run after the post_shutdown_phase (the arrow comes from there)… I assume that it also will not enter extract until the run_phase is complete (the UVM phasing breakdown for tasks is relatively new so this is how it always worked.)
In reply to wpiman:
The message I mentioned comes from the UVM base classes. It is not coded individually.
I see you are working with the sub-pahses of the run_phase, i.e. reset_phase, config_phase etc.
Do you have implementations for all these phases and why are you using them?
I belove your environmet hangs somewhere there.
In reply to chr_sue:
I don’t use all of them. I use reset, configure, main, and shutdown. Rather than using a virtual sequencer in the run phase-- you just start a sequence in a particular phase. For example, if you want to setup your DUT-- you can run a register configuration sequence in that phase. Then in your main phase, you start your sequences for driving your main data, and then in your shutdown phase-- you can read the status registers and get them against a model.
Been doing this for years with UVM 1.1d and never had this issue. Much cleaner than using virtual sequencers.
I switched back to the UVM 1.1d library and the problem goes away.
I don’t see anything anywhere in the 1.2 change log that says this should have changed…
In reply to wpiman:
There are certain relationships between theses phases you have to consider. In most cases this is not really necessary. You’ll find solutions using simply run_phase.
In reply to wpiman:
Ok, I’ve solved this issue… I’ll document it here in case anyone else runs into this.
In the new 1.2 uvm_report_server (line 847), it appears that the UVM report only prints if the verbosity level is UVM_LOW or greater. The module appears to be a major rewrite since 1.1d.
847 uvm_info("UVM/REPORT/SERVER",UVM_STRING_QUEUE_STREAMING_PACK(q),UVM_LOW)
Depending on your verbosity switch, you may not see this message. In the last revision, it didn’t rely on the uvm_info macro…
I’d argue this should be UVM_NONE or simply not make use of the Macro…
In reply to wpiman:
Thanks for updating us! Have you considered filing a Mantis with your suggestion? I like your argument, makes sense to me.
Regards
Srini
In reply to Srini @ CVCblr.com:
In reply to wpiman:
Thanks for updating us! Have you considered filing a Mantis with your suggestion? I like your argument, makes sense to me.
Regards
Srini
Is this some sort of bug tracker with the Accellera group? I’d be happy to. I will try emailing you to get details…