In reply to chr_sue:
I don’t use all of them. I use reset, configure, main, and shutdown. Rather than using a virtual sequencer in the run phase-- you just start a sequence in a particular phase. For example, if you want to setup your DUT-- you can run a register configuration sequence in that phase. Then in your main phase, you start your sequences for driving your main data, and then in your shutdown phase-- you can read the status registers and get them against a model.
Been doing this for years with UVM 1.1d and never had this issue. Much cleaner than using virtual sequencers.
I switched back to the UVM 1.1d library and the problem goes away.
I don’t see anything anywhere in the 1.2 change log that says this should have changed…