UVM analysis port inside Checker construct

UVM
1

Hi,
I am trying to build a system level coverage model based on sequences/properties and cover directives. The plan is plug this into UVM testbench and measure coverage for the scenarios intended.
I understand that the place holder to define and instantiate the model can be of the following :

  1. Interface
  2. Checker
  3. Module
    Being system level properties, some of the information required to populate sequence/property variables is not directly based on signals, instead abstracted at a higher level(packets, line states etc). These info are available with the existing monitors and scoreboards (UVM based) in the testbench.
    If I want to pass these abstract information to one of the above constructs, is it possible to do it with analysis port ↔ analysis_imp approach ? If yes, please provide an example (if possible)

Thanks,
Sharath

2

In reply to schandran:

I understand that the place holder to define and instantiate the model can be of the following :

  1. Interface
  2. Checker
  3. Module

coverage model can be defined and instantiated in interface, checker and module. But it doesn’t mean that the system level coverage model has to be placed in the upper constructs. Instead, a typical place to instantiate system level coverage model is under UVM environment, such as deriving a coverage model class from uvm_subscriber. In UVM environment, you have all the accesses to DUT signals through virtual interface and receive transactions from monitor through TLM communication.

3

In reply to schandran:

Your coverage model seems to be an Assertion coverage model. It follows from your description. Assertions can not be implemented in Class-based components, i. e. it is limited to
(1) interfaces
(2) modules
(3) programs.

Covergroups (functional coverage) can be implemented in clas-based components and this is the prfered place.