UVM analysis port inside Checker construct

In reply to schandran:

I understand that the place holder to define and instantiate the model can be of the following :

  1. Interface
  2. Checker
  3. Module

coverage model can be defined and instantiated in interface, checker and module. But it doesn’t mean that the system level coverage model has to be placed in the upper constructs. Instead, a typical place to instantiate system level coverage model is under UVM environment, such as deriving a coverage model class from uvm_subscriber. In UVM environment, you have all the accesses to DUT signals through virtual interface and receive transactions from monitor through TLM communication.