Testing Read only Registers

UVM
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1

Morning all,

death match with the register abstraction layer continues!

After giving up on the bit bash sequences (poor uvm implmementation of reserved fields) i have written my own access test.
I am now curious about testing read only register.

For example, if we have a version register used to indicate the version of hdl code.
From a register perspective this would be like holding its inputs at set levels forever and ever. If i was to create a test to ensure the read only capability of the register i would create a backdoor write or poke then a front door read?

So what if i want to change the read-only register from the other side of the register? These are only status pins or hardcoded pins. Can i use the back door for one cycle?
I know want to create another uvc just for two or three pins.

Any thoughts?

2

Hi Phill,

Of course you can use the backdoor access to these register’s. Indeed the backdoor_write function is available for Read-Only registers.

Just you need to make sure that hdl_path is correct.

Thanks,
Vaibhav

3

In reply to Vaibhav Tekale:

Vaibhav,

thanks for getting back to me.

The problem i have is that if the pins are hard coded, the backdoor poke (or write) only forces the signals to what i want for a clock cycle until the input pins are re-assigned.
This also applies to registers that are RO on the software side and WO on the hardware side.

What does backdoor_write do that is different from write or poke?

4

Ok well i guess i answered my own questions again.

The truth is that via the register model you can only test the sw interface.
Unless i have another UVC to drive the pins from the register block there is no point in the approach above.

if i back door write, the data will be over written on the next clock with the data actually on the pins of the register.

The answer was to change how i tested the read only side of the register.