Simulation syntax error

UVM
1 
mvlog: *E,NOIPRT (apb_agent.sv,15|13): Unrecognized declaration 'apb_monitor' could be an unsupported keyword, a spelling mistake or missing instance port list '()' [SystemVerilog].
(`include file: apb_agent.sv line 15, `include file: apb_pkg.sv line 17, file: testbench.sv line 14)
`uvm_component_utils(apb_env);

Can Anyone help with this error how to resolve it?

2

In reply to pinnuk:

Looks like you did not compile the class apb_monitor.

3

In reply to chr_sue:

I Have included in the package and that package I am importing in testbench top

4

In reply to pinnuk:

But you might not compile in the right order. Please double check.

5

In reply to chr_sue:

package apb_pkg;

// Import the UVM class library  and UVM automation macros
import uvm_pkg::*;
`include "uvm_macros.svh"

`include "apb_rw.sv"
`include "apb_sequence.sv"
`include "apb_sequencer.sv"
`include "apb_driver.sv"

`include "apb_monitor.sv"
`include "apb_scoreboard.sv"
`include "apb_agent.sv"
`include "apb_env.sv"
`include "apb_test.sv"


endpackage : apb_pkg

this is my compilation order

6

In reply to pinnuk:

The order is OK. Maybe there is a typo somewhere wrt apb_monitor.

7

In reply to pinnuk:

Check the monitor class name in "`include “apb_monitor.sv”.

8

In reply to Rahulkumar:
This is the monitor code in the beginning

class apb_monitor extends uvm_monitor;

  `uvm_component_utils(apb_monitor)
//  virtual apb_if.passive vif;
 virtual apb_if vif;
       apb_rw tr;

  ///Monitor writes transaction objects to this port once detected on interface
  uvm_analysis_port#(apb_rw) ap;

This is the agent code. I am getting the error at the line “apb_monitor mon;”

class apb_agent extends uvm_agent;

   // sequencer, driver and monitor components for the APB interface
  apb_sequencer sqr;
  apb_master_drv drv;
  apb_monitor mon;

   virtual apb_if  vif;

   `uvm_component_utils_begin(apb_agent)
      `uvm_field_object(sqr, UVM_ALL_ON)
      `uvm_field_object(drv, UVM_ALL_ON)
      `uvm_field_object(mon, UVM_ALL_ON)
   `uvm_component_utils_end
   
   function new(string name, uvm_component parent = null);
      super.new(name, parent);
   endfunction
9

In reply to pinnuk:

This looks OK.
Could you please post some example simplified code to validate the structural issue you are facing.

10

In reply to chr_sue:
i did not get the context of question. Could you please elaborate?

11

In reply to pinnuk:

This EDAplayground example works fine.
But I want to see the same with the apb components and the apb package file.
I’m interested in the structural aspects and do not want to know your run_phase implementations.

12

In reply to chr_sue:

13

In reply to pinnuk:

The first link is fien, but I cannot access the 2nd link.

14

In reply to chr_sue:
I have modofied the 1st link to use a package.
It works here

Please not you are using capital leters in the file name.
SV is case sensitive!

15

In reply to chr_sue:

Thanks but I could not get the what is wrong with my original environment where I am getting error. Still it is there.

16

In reply to pinnuk:

Look to the names including file names. SV is case sensitive!