Simulation syntax error

UVM
8

In reply to Rahulkumar:
This is the monitor code in the beginning

class apb_monitor extends uvm_monitor;

  `uvm_component_utils(apb_monitor)
//  virtual apb_if.passive vif;
 virtual apb_if vif;
       apb_rw tr;

  ///Monitor writes transaction objects to this port once detected on interface
  uvm_analysis_port#(apb_rw) ap;

This is the agent code. I am getting the error at the line “apb_monitor mon;”

class apb_agent extends uvm_agent;

   // sequencer, driver and monitor components for the APB interface
  apb_sequencer sqr;
  apb_master_drv drv;
  apb_monitor mon;

   virtual apb_if  vif;

   `uvm_component_utils_begin(apb_agent)
      `uvm_field_object(sqr, UVM_ALL_ON)
      `uvm_field_object(drv, UVM_ALL_ON)
      `uvm_field_object(mon, UVM_ALL_ON)
   `uvm_component_utils_end
   
   function new(string name, uvm_component parent = null);
      super.new(name, parent);
   endfunction