Resetting the DUT causing the uvm sequencer reset

Hi All,

I have facing the strange issue. I am doing the reset in between the transactions and reset went well. After that I tried to send the transaction just to clean exit from the test.
It been observed that am getting below fatal error:
UVM_FATAL: ahb_inst.ahb_read [SEQ] neither the item’s sequencer nor dedicated sequencer has been supplied to start item in ahb_inst.ahb_read

The same sequence before reset is working fine and we are able to start sequencer and initiate the transaction.

Can anyone please suggest?

In reply to yuvraj khare:

I do not know your testbench environment. But this environment should not be modified by asserting a reset signal. There is something else wrong. Please provide some more detials/code to help you.
What is ‘ahb_inst.ahb_read’?

In reply to chr_sue:

ahb_inst is the handle of ahb_transation sequence and ahb_read is the task in sequence.

Using below code in base test as:

virtual task main_phase(uvm_phase phase);
phase.raise_objection(this);
super.main_phase(phase);


ahb_inst.set_sequencer(env_inst.virtual_sequencer.sequencer_handle);

endtask:main_phase

In reply to yuvraj khare:

Two things:
(1) Don’t use the run_phase subphases use run_phase instead.
(2) To start a sequence execute the following command:

ahb_inst.start(<sequencer object to run this sequence>);

You do not need the set_sequencer command.

In reply to chr_sue:

Thanks.
Let me try and let you know the result.

In reply to yuvraj khare:

Same Fatal error coming after using the :
ahb_inst.start();

UVM_FATAL: ahb_inst.ahb_read [SEQ] neither the item’s sequencer nor dedicated sequencer has been supplied to start item in ahb_inst.ahb_read.

Didn’t get why the same sequence is running correctly and doing configuration before RESET.
I have checked that VIP is come out of reset.

In reply to chr_sue:

Thanks. It solved apprecited a lot.