Resetting the DUT causing the uvm sequencer reset

In reply to chr_sue:

ahb_inst is the handle of ahb_transation sequence and ahb_read is the task in sequence.

Using below code in base test as:

virtual task main_phase(uvm_phase phase);
phase.raise_objection(this);
super.main_phase(phase);


ahb_inst.set_sequencer(env_inst.virtual_sequencer.sequencer_handle);

endtask:main_phase