RAL:: uvm_reg vs uvm_mem

UVM
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1

Hi,

UVM RAL supports both uvm_reg and uvm_mem for registers and memories. can anyone explain what is the difference between uvm_reg and uvm_mem?
I know about configuring uvm_reg, can any share code for configuring uvm_mem? How it is differ from uvm_reg?

Thanks in advance.

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In reply to mitesh.patel:

There are two basic differences:

  1. uvm_mem has no shadow (mirror or desired) storage. Only the RTL holds state. This means access is via read/write/peek/poke API methods. uvm_reg has additional get/set/update/mirror/predict.
  2. A register occupies one address. A memory occupies a range of addresses.

You could model a memory with uvm_reg by declaring one register and then declaring a block of multiple register instances, but that would create too much overhead. uvm_mem gives you access to the same bus abstraction layer and address mapping as uvm_reg without the overhead.

See Registers/ModelStructure | Verification Academy for more details.

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In reply to dave_59:

Thanks Dave for response.