Hi all,
I'm trying to configure and verify my DUT via RAL. First, I write certain values to registers(or memory) through frontdoor access. Next, I read it through backdoor access and compare those values with the expected values.
class cfg_seq extends uvm_reg_sequence#(uvm_sequence#(data));
// utils macro and constructor not shown
ral_block_host_regmodel regmodel;
virtual task body();
uvm_status_e status;
uvm_reg_data_t data;
if(starting_phase != null)
starting_phase.raise_objection(this);
regmodel.LOCK.read(.status(status), .value(data), .path(UVM_BACKDOOR), .parent(this));
if (data != 'hffff) begin
`uvm_fatal("RAL_ERR", $sformatf("LOCK is %4h instead of 'hffff", data));
end
regmodel.LOCK.write(.status(status), .value('1), .path(UVM_FRONTDOOR), .parent(this));
regmodel.LOCK.read(.status(status), .value(data), .path(UVM_BACKDOOR), .parent(this));
if (data != '0) begin
`uvm_fatal("RAL_ERR", $sformatf("LOCK is %4h instead of 'h0000", data));
end else begin
`uvm_info("RAL_TEST", $sformatf("LOCK is %4h the expected value is 'h0000", data), UVM_MEDIUM);
end
// Others register configurations not shown
//===Verify memory by walking ones algorithm===
// Write walking ones to the RAM
for (int i=0; i<4096; i++) begin
regmodel.RAM.write(.status(status), .offset(i), .value(16'b1 << i%16), .path(UVM_FRONTDOOR), .parent(this));
end
// Read back from the RAM and check the pattern
for (int i=0; i<4096; i++) begin
regmodel.RAM.read(.status(status), .offset(i), .value(data), .path(UVM_BACKDOOR), .parent(this));
if (data != (16'b1 << i%16)) begin
`uvm_fatal("RAL_ERR", $sformatf("RAM is %4h instead of %4h", data, 16'b1 << i%16));
end
end
`uvm_info("RAL_TEST", "RAM contains the expected values", UVM_MEDIUM);
if(starting_phase != null)
starting_phase.drop_objection(this);
endtask
endclassEverything works fine except writing memory through frontdoor access. The valus read back from the RAM is the residual value instead of the expected.
At first, I thought there is something wrong with the frontdoor path;but, other writing through frontdoor accesse for registers worked fine. Hence, I did some experiments:
- FRONTDOOR write to the RAM, then FRONTDOOR read from the RAM
- BACKDOOR write to the RAM, then FRONTDOOR read from the RAM
- BACKDOOR write to the RAM, then BACKDOOR read from the RAM
Finally, I figured out that only "BACKDOOR write" will success.
I googled and found some similar problems:
- Issue when UVM Reg Frontdoor write followed by Backdoor read
- UVM Reg Frontdoor and Backdoor accesses
- difference in backdoor and frontdoor accessing of memory
These posts pointed out that the possible reason causes this may be the DUT or timing problem.
I suppose the issue is caused by timing problem(i.e., read operations were performed before write operations finished). If so, is there any mechanism can prevent from this issue? Or maybe isn't the timing problem?
I know that using backdoor access for memory is recommended, but I still want to know if there is a proper way to access memory through frontdoor access.
Any advise or hint is appreciated.
Thanks in advance,
Sheila
