Pass variable from test to sequence

UVM
1

Hello Experts,

I need your valuable suggestion on this error.
Im trying to pass a variable from one sequence to another within a test.

class seq2;
    bit [6:0] var;
    task body()
        uvm_config_db#(bit [6:0])::get(this,"*","var", var);
    endtask
endclass

class seq1;
    rand bit [6:0] var;
    task body()
        assert(this.randomize());
    endtask
endclass

class test extend base_test;

    task run_phase

        seq1.start();
        uvm_config_db #(bit [6:0])::set(this,"*","var",seq1.var );
        
        seq2.start();
       
    endtask : run_phase

endclass

====================================
Error

ncvlog: *E,TYCMPAT (/test.sv,88|42): formal and actual do not have assignment compatible data types (expecting datatype compatible with ‘class uvm_pkg::uvm_component’ but found ‘class test_pkg::seq2’ instead).

please advice.

2

In reply to harshavs:


//It can be done without using config db 
class test extend base_test;
 
    task run_phase
 
        seq1.start();
        //uvm_config_db #(bit [6:0])::set(this,"*","var",seq1.var );
 
        seq2.var = seq1.var; // OR ser2.randomize() with { var == seq1.var; };
        seq2.start();
 
    endtask : run_phase
 
endclass
3

In reply to Rahulkumar:

Hello Rahul,

Thanks for you response, I did consider the method you mentioned, but its more hardline code, I want something robust.
Reason being, I have to move common sequences to base test and run them by default.
I want to set certain variables in my extended tests and retrieve in sub/parent/child/nested sequences as and when required.

Generally set/get get should do the job, I do not understand the error message, why are they type incompatible.

Br/Harsha

4

In reply to harshavs:


static function bit get(uvm_component cntxt, 
                        string inst_name,
                        string field_name,
                        inout T value	)

uvm_config_db get and set won’t work in the uvm_sequence as 1st argument context should be uvm component and uvm_sequence is uvm_object.

Only one way left is through sequencer, you can do it.

  1. add get method inside the sequencer (which is uvm_component)
  2. access the variable inside the sequence through sequencer handle.


//sequencer
class my_sequencer extends uvm_sequencer#(my_transaction);
  bit [6:0] my_var;
  `uvm_component_utils(my_sequencer)
  
   virtual function void build_phase (uvm_phase phase);
       super.build_phase(phase);
       if (! uvm_config_db#(bit [6:0])::get(this,"*","my_var", my_var))
         `uvm_error (get_type_name(), "Did not get my_var")
   endfunction : build_phase
  
endclass : my_sequencer 


//sequence
    class my_seq extends uvm_sequence;
      `uvm_object_utils (my_seq)
      `uvm_declare_p_sequencer (my_sequencer)

      function new (string name = "my_virtual_seq");
        super.new (name);
      endfunction

      task body();
        ...
        a = p_sequencer.my_var; 
        ...
      endtask

    endclass

//test case
class test extend base_test;
   bit[6:0] my_var;
   my_seq  my_seq_inst;

   virtual function void build_phase (uvm_phase phase);
      super.build_phase (phase);
      uvm_config_db#(bit [6:0])::set(this,"*","my_var", my_var);
   endfunction

  virtual task run_phase (uvm_phase phase);
     super.run_phase  (phase);
     //.....
     seq1.start();

    //..........
     my_var = seq1.my_var;

    my_seq_inst.start()
    //.........
  endtask

 
endclass
5

In reply to harshavs:

Just pass null instead of this.

uvm_config_db#(bit [6:0])::get(null,"*","var", var);
6

In reply to dave_59:

In reply to harshavs:
Just pass null instead of this.

uvm_config_db#(bit [6:0])::get(null,"*","var", var);

Thanks Dave.

7

But why to pass null

8

The first argument to uvm_config_db: get/get must be derived from uvm_component which uvm_sequence is not. That argument represents the highest level of the component hierarchy where the setting applies. You could use the sequencer handle if these are all sequences running on the same sequencer. But using null representing the root/top of the hierarchy might be better if you do not want to restrict the setting to a single sequencer.

1 Like
10

The problem with uvm_config_db has been that it contributes to a significant slow-down of TB.
Chris Spear recommends same approach as RahulPatel by using OOP-style.

Another way is to set and get using the uvm_resource_db.
http://www.sunburst-design.com/papers/CummingsDVCon2023_uvm_resource_db_API.pdf
It can pass any type of variables from components or objects. Again slow but you don’t need to deal with the murky m_sequencer.

11

Hi RahulPatel,
Here you have set uninitialized my_var in build_phase of test.
Will my_var in my_sequencer get updated by seq1.my_var as u are assigning my_var=seq1.my_var in run phase of test?