Pass variable from test to sequence

UVM
4

In reply to harshavs:


static function bit get(uvm_component cntxt, 
                        string inst_name,
                        string field_name,
                        inout T value	)

uvm_config_db get and set won’t work in the uvm_sequence as 1st argument context should be uvm component and uvm_sequence is uvm_object.

Only one way left is through sequencer, you can do it.

  1. add get method inside the sequencer (which is uvm_component)
  2. access the variable inside the sequence through sequencer handle.


//sequencer
class my_sequencer extends uvm_sequencer#(my_transaction);
  bit [6:0] my_var;
  `uvm_component_utils(my_sequencer)
  
   virtual function void build_phase (uvm_phase phase);
       super.build_phase(phase);
       if (! uvm_config_db#(bit [6:0])::get(this,"*","my_var", my_var))
         `uvm_error (get_type_name(), "Did not get my_var")
   endfunction : build_phase
  
endclass : my_sequencer 


//sequence
    class my_seq extends uvm_sequence;
      `uvm_object_utils (my_seq)
      `uvm_declare_p_sequencer (my_sequencer)

      function new (string name = "my_virtual_seq");
        super.new (name);
      endfunction

      task body();
        ...
        a = p_sequencer.my_var; 
        ...
      endtask

    endclass

//test case
class test extend base_test;
   bit[6:0] my_var;
   my_seq  my_seq_inst;

   virtual function void build_phase (uvm_phase phase);
      super.build_phase (phase);
      uvm_config_db#(bit [6:0])::set(this,"*","my_var", my_var);
   endfunction

  virtual task run_phase (uvm_phase phase);
     super.run_phase  (phase);
     //.....
     seq1.start();

    //..........
     my_var = seq1.my_var;

    my_seq_inst.start()
    //.........
  endtask

 
endclass