Parameterized class error

UVM
1

I have a class defined as below -


class base_sequencer #(type REQ = base_seq_item,
                       type BYPASS = base_seq_item,
                       type SUBSCRIBER = base_sequencer)
extends uvm_sequencer #(REQ);

Is there any problem with the way “type SUBSCRIBER = base_sequencer” is declared in the above code? Is this a legal way of declaring or does this result in a recursive call?

I want to create 2 objects of the above class type, one of which I want to parameterize SUBSCRIBER with another class type while for the other object I don’t want to. Is this possible with the above code?

What is the difference of the above code with this -


class base_sequencer #(type REQ = base_seq_item,
                       type BYPASS = base_seq_item,
                       type SUBSCRIBER)
extends uvm_sequencer #(REQ);
2

In reply to tpan:

This first is a recursive definition. When you reference base_sequencer in the first code block, it is the same as writing

class base_sequencer #(type REQ = base_seq_item,
                       type BYPASS = base_seq_item,
                       type SUBSCRIBER = base_sequencer#(REQ,BYPASS,base_sequence#(REQ,BYPASS,base_sequence#(...)))))))
extends uvm_sequencer #(REQ);

We would need to see more of what you want to do with the body of the class to know what to recommend.

3

Thanks for the response, Dave. How about the 2nd syntax, does that work?

I am trying to make the following implementation.


`uvm_analysis_imp_decl(_bypass);
class base_sequencer #(type REQ = base_seq_item,
                       type BYPASS = base_seq_item,
                       type SUBSCRIBER)
extends uvm_sequencer #(REQ);

    `uvm_component_param_utils(base_sequencer#(REQ, LOOPBACK_REQ, SUBSCRIBER));

     uvm_analysis_imp_bypass #(BYPASS, SUBSCRIBER) bypass_port;

     //! Subscriber function for bypass transaction
     function void write_bypass (BYPASS trans);
          //Logic to receive and store the trans
     endfunction : write_bypass

I have sequences that are reactive, i.e they need to get driven based on transactions seen from other agents. I am using the other agent’s sequencer as the subscriber. And the other agent’s transaction type is ‘BYPASS’.

So let’s say the names of the agents are base_agent and other_agent. This is what I have in my env -


function void connect_phase (uvm_phase phase);
    super.connect_phase(phase);
    other_agent.monitor.mon_analysis_port.connect(base_agent.sequencer.bypass_port);
endfunction : connect_phase

Now I also have sequences which don’t need these connections. For these I don’t want to change the SUBSCRIBER type and leave it as it is.

4

In reply to tpan:

Only the transaction class type needs to be compatible to make an analysis port connection. You should be able to write

class base_sequencer #(type REQ = base_seq_item,
                       type BYPASS = base_seq_item)
extends uvm_sequencer #(REQ);

typedef base_sequencer#(REQ, LOOPBACK_REQ) this_type;
 
    `uvm_component_param_utils(this_type);
 
     uvm_analysis_imp_bypass #(BYPASS, this_type) bypass_port;