Memory modeling for TEST BENCH

UVM
,
1

Hi All,

I want to model a memory for TEST BENCH . Does UVM provide any special way to model it ?? This memory is not related to DUT .
Its like system memory outside the DUT

Thanks
CB Singh

2

There is nothing specific in UVM for modeling memories. As a general comment, memories are probably best modeled with a dynamic array in SystemVerilog. The real UVM question is where you want to put the memory and what you want to do with it.

3

In reply to tfitz:

In SOC verification . Memory model need to be modeled in TESTBENCH as system memory , Its like a common problem . In UVM there is nothing to model this memory ??

4

In reply to Chandra Bhushan Singh:

I guess I don’t understand your question well enough to answer it.
If you want to use UVM to create a component that will model system memory outside of (but presumably connected to) your DUT, you can. This would be what we call a slave agent in the Cookbook, where you have a testbench component that connects either to your DUT or to something else in your testbench. Does that help?