Making a testbench before the design

UVM
1

Hi

I am required to make a testbench in UVM without a design or DUT (to start with). Can you guys advise me how to go about it?.. I am relatively new to this.

I would ideally would like to use the same testbench when the design is there and just instantiate it…

If you can also point me to any working examples and resources please that would be great…Or any book in UVM that deals with similar thing

Many thanks

2

In reply to jennra:

This is the normal way how projects starting the verification. Desig nand testbench development starts at the same time. The only thing you need is the information about the functional interfaces used by the design, then you can start to develop your agents, sequences and the first tests.

3

In reply to jennra:

You can certainly write a dummy DUT that is empty, build all your interfaces, and build everything you need to get to the run_phase of your test. What you do after that is very dependent on the design. You supposedly have enough information to predict what the design is supposed to do, so you can use those same predictors to generate the outputs of the DUT, (in the ideal case).

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In reply to lockheed-hughes:

Thanks very much for all your replies.

Is their a white paper which describes making a UVM testbench without a DUT or something?(ideally) or if not it describes be System verilog/vhdl testbench without a DUT?

Many thanks

5

In reply to jennra:

If you lnow the interface of your DUT then there is no difference between making a testbench having a complete DUT or not. Ther is nothing specific for this case.