In reply to lockheed-hughes:
Thanks very much for all your replies.
Is their a white paper which describes making a UVM testbench without a DUT or something?(ideally) or if not it describes be System verilog/vhdl testbench without a DUT?
Many thanks
In reply to lockheed-hughes:
Thanks very much for all your replies.
Is their a white paper which describes making a UVM testbench without a DUT or something?(ideally) or if not it describes be System verilog/vhdl testbench without a DUT?
Many thanks