Logic to rsp asserted 8clks after req

UVM
1

Hi,
I am trying to implement logic in driver class to check that rsp is asserted 8 clks after valid is asserted. Valid could be back to back.
Is there a better way to write it?


task run_phase();
   forever begin
      @(posedge clk)
      if(valid)begin
         fork
            req_rsp_8_clks();
         join_none
      end
   end
endtask

task automatic req_rsp_8_clks();
   repeat(8)
   @(posedge clk);
   vif.rsp = 1'b1;

   @(negedge clk)
   vif.rsp = 1'b0;

endtask
2

In reply to UVM_SV_101:

I do not understand the question. Are you do a “check” on rsp or do you need to drive it? And do you mean to say that the 8 clock cycles could be overlapping?

3

In reply to UVM_SV_101:

Hi,
I am trying to implement logic in driver class to check that rsp is asserted 8 clks after valid is asserted. Valid could be back to back.
Is there a better way to write it?


task run_phase();
forever begin
@(posedge clk)
if(valid)begin
fork
req_rsp_8_clks();
join_none
end
end
endtask
task automatic req_rsp_8_clks();
repeat(8)
@(posedge clk);
vif.rsp = 1'b1;
@(negedge clk)
vif.rsp = 1'b0;
endtask

Your code is driving the rsp signal.
If you want to check the correct behavior of the rsp you might use a SV Assertion checker.

4

In reply to dave_59:

In reply to UVM_SV_101:
I do not understand the question. Are you do a “check” on rsp or do you need to drive it? And do you mean to say that the 8 clock cycles could be overlapping?

Hi dave,
Sorry for the confusion, I need to drive rsp 8 clks after I see valid. Yes 8 clks could be overlapping (consecutive valid)

5

In reply to chr_sue:

In reply to UVM_SV_101:
Your code is driving the rsp signal.
If you want to check the correct behavior of the rsp you might use a SV Assertion checker.

Thats correct my code is driving the rsp signal. I am creating another thread for how to writing assertion to check the same…

6

In reply to UVM_SV_101:
Use non-blocking assignments.

task run_phase();
   forever begin
      @(posedge clk iff valid)
       vif.rsp <= repeat (8) @(posedge clk) 1'b1;
       vif.rsp <= repeat (8) @(negedge clk) 1'b0;
   end
endtask