Int casting of negated bit - unexpected result

UVM
, , ,
1 

  `uvm_info(get_name(), $sformatf("int'(~1'b0) = %d",int'(~1'b0)), UVM_LOW)

results in

UVM_INFO testbench.sv(28) @ 0: reporter [m_obj] int’(~1’b0) = -1

This wasted some of my time as I assumed this would return 1.
So, how come it returns -1?

Isn’t ~1’b0 = 1’b1, and then int’(1’b1) = 32b’1?

Where did the minus come from?

Thanks,
Nimrod

2

In reply to nimrodw:

The rules for evaluating expressions in Verilog have always been that the widths of operands get extended based on their context before applying the operator. The 1-bit operand 1’b0 feted extended to 32’b0, then the bitwise negation ~ happens.

If you want the result you intended, us a logical ! instead of bitwise ~.