How to turnoff the constraint that is present in another file .?

UVM
,
1

Here is a sample code of what I’m working on

class c_cfg extends uvm_object;
	rand bit c_bit;
	
	constraint c_turnoff {
		c_bit == 1'b0;
	}
	...........

endclass: c_cfg

2nd file

class b_cfg extends uvm_object;

	rand c_cfg	cfg_c;
	........
	........

endclass: b_cfg

main file

class a_cfg extends b_cfg;

// I want to overwrite the constraint in c_cfg here.
// I want that to be 1

endclass: a_cfg

I tried overwriting the constraint in c_cfg by using the same constraint name in a_cfg, but it doesn’t solve (I guess it is because in c_cfg and not in b_cfg) simulator is not able to solve the constraint. Then tried cfg_c.c_turnoff.constraint_mode(0); in the new function in a_cfg, but it still considers the constraint in c_cfg.

Can someone suggest how to do that.

Thanks

2

In reply to aalpa23:

Do you really need to make this random?

How about

class c_cfg extends uvm_object;
  bit c_bit = 0;
...
class a_cfg extends b_cfg;
function new(string name);
  super.new(name);
  c_cfg.c_bit = 1;
...
3

In reply to aalpa23:

how about call post_randomize like this:

class a_cfg extends b_cfg;

// I want to overwrite the constraint in c_cfg here.
// I want that to be 1
function void post_randomize();
cfg_c.c_bit = 1;
endfunction: post_randomize

endclass: a_cfg

when you call c_cfg’s instance randomize(), varibale c_bit can be set to 1