How to take input from the transcript in Questasim or generally in any other Tool using verilog / Systemverilog / UVM?

UVM
, , ,
1

In C-language we use scanf() to take the input, in python we use input() function where we can also add some customized statement to convey the description of what needs to be the input. Similarly what can be used in SV/ UVM to take the input from the user?

2

In reply to Verif@dj:

See section 21.3 File input/output system tasks and system functions in the IEEE 1800-2017 SystemVerilog LRM

3

Thank you dave_59.I have been struggling with this for many days. Thanks a lot