Getting UVM_ERROR for Register Abstraction Layer , But UVM_ERROR's At the end of simulation shown as 0

UVM
,
1

Getting UVM_ERROR as follows during simulation :

UVM_ERROR: get: unable to locate hdl path top.svr.sw_up.device.MAN_REGS.rdt_life_tim

Either the name is incorrect, or you may not have PLI/ACC visibility to that name

UVM_INFO /home/shreemant/svn_chkout_300715/40G_ExpEth_Verif/40g_expether/testbench/mode_3/sequences/life_timer_reg_value_change.svh(34) @ 0ns: uvm_test_top.top_env.srv_env.pcie_agent.sequencer@@life_timer_reg_value [life_timer_reg_value_change] Value of LIFE_TIMER_REG_S read from the DUT for server is 00000000

UVM_ERROR: set: unable to locate hdl path (top.svr.sw_up.device.MAN_REGS.rdt_life_tim)

Either the name is incorrect, or you may not have PLI/ACC visibility to that name

//----------------------------------------------------------------------------------------------------

But at the end shown as:

— UVM Report Summary —

** Report counts by severity

UVM_INFO : 4187

UVM_WARNING : 1

UVM_ERROR : 0

UVM_FATAL : 0

** Report counts by id

[EXPETHINTF] 6

[LEDINTF] 27

[PCIE REG Block] 67

[PEB_READWRITE_SEQ] 2

[Questa UVM] 2

[RASINTF] 24

[RNTST] 1

[TEST_DONE] 1

[TEST_MODE4_026] 1

[TPRGED] 1

[UVMTOP] 1

[connecting analysis component] 38

[creating analysis component] 38

[creating ap] 50

[creating component] 2

2

In reply to shreemant.vats:

Hi Shreemanth,

May be the issue with the tool.If you found a solution ,paste it here.

Thanks,
-Murali