Hi,
I am trying to make verification plan using UVM.
While instantiating my RTL code written in VHDL that has generic of one bit STD_LOGIC. I want to change the generic using define or parameters in my UVM testbench. While changing the values of generic through define or parameter. It is not reflecting in the output in the simulation. I am getting the same results with different generic values.
It certainly reflects the value if I change the data type of one bit STD_LOGIC generic to STD_LOGIC_VECTOR(0 DOWNTO 0).
Can anybody help me resolving the issue?
In reply to Mayank98:
It is not clear what you are asking without showing any code. How could you possibly change a VHDL generic with a SystemVerilog `define?
Here’s the RTL code of design that has a generic of std_logic:
//ENTITY serial_data IS
GENERIC( ENDIAN : std_logic := ‘1’)
IF(ENDIAN = ‘1’)
THEN
out<= read_data(to_integer(unsigned(counter)));
ELSE
out<= read_data(31 - to_integer(unsigned(counter)));
END IF;//
Here’s the tb top file of my UVM TB where I am instantiating my DUT and supplying parameter to the generic.
parameter ENDIAN=1’b1;
rs485_transmitter_01 #(.ENDIAN(P_ENDIAN))
But everytime I am simulating else statement of the RTL code is executing irrespective of keeping ENDIAN as 1 or 0.
In reply to Mayank98:
There is no `define in the code you show.
Mixed language simulation may have tool specific issue, and this forum is not for that.
I suggest contacting your tool vendor for support.
Hello Dave,
I would like to restate my problem statement described above for your clarification.
Problem Statement:
I have created a testbench using System Verilog for testing a VHDL DUT.
The VHDL DUT as described below has generic mappings.
ENTITY uart_tx IS
GENERIC(
G_ENDIAN : std_logic := ‘1’; – Little or Big Endian
G_SR_DELAY : std_logic_vector(14 DOWNTO 0):= “000000000011111”;
G_PARITY_EN : std_logic := ‘0’ – Parity bit transmission enable
);
PORT (
i_clk : IN std_logic; – System Clock
i_rst_n : IN std_logic; – Reset (Active Low)
o_tx_data : OUT std_logic – Transmission output serial data
);
END uart_tx;
Instantiation of VHDL DUT (uart_tx.vhd) in System Verilog testbench (tb_top.sv) is described below.
uart_tx #(
.G_ENDIAN (P_ENDIAN), //: std_logic ; – Selection of Big Endian and Little Endian
.G_SR_DELAY (P_SR_DELAY), //: std_logic_vector(14 DOWNTO 0); – Set-up and Recovery time
.G_PARITY_EN (P_PARITY_EN) //: std_logic – Parity bit transmission enable
)
//==========================================================================
// VHDL PORT MAPPING
//==========================================================================
dut(
.i_clk (tb_top_vif.clk ),//: System Clock
.i_rst_n (tb_top_vif.rst_n),//: Reset (Active Low)
.o_tx_data (tb_top_vif.tx_data) //: Transmission output serial data
);
I have observed issue while modifying the generic map values “P_ENDIAN” and “P_PARITY_EN” which are defined in “tb_defines.sv” as described below
`define P_ENDIAN 1 //Selection of Big Endian and Little Endian
`define P_SR_DELAY 31 // Set-up and Recovery time
`define P_PARITY_EN 1
PROBLEM STATEMENT:
Although I change the value of “P_ENDIAN” and “P_PARITY_EN” as 1, it is observed that no matter what value I assign here the VHDL DUT seems to be taking the value 0. We don’t observe any issues with modifying the GENERIC values in VHDL based test environment (i.e. both DUT and TB are in VHDL)
We are currently using Questasim 10.2C as a simulator tool.