Getting issue in decoding the one bit STD_LOGIC generic datatype

UVM
3

Here’s the RTL code of design that has a generic of std_logic:

//ENTITY serial_data IS
GENERIC( ENDIAN : std_logic := ‘1’)

IF(ENDIAN = ‘1’)
THEN
out<= read_data(to_integer(unsigned(counter)));
ELSE
out<= read_data(31 - to_integer(unsigned(counter)));
END IF;//

Here’s the tb top file of my UVM TB where I am instantiating my DUT and supplying parameter to the generic.

parameter ENDIAN=1’b1;
rs485_transmitter_01 #(.ENDIAN(P_ENDIAN))

But everytime I am simulating else statement of the RTL code is executing irrespective of keeping ENDIAN as 1 or 0.