I have VIP in UVM and that’s instatiated in vmm env.
I have one assertion module which present in UVM VIP written in verilog. I have hooked up those to VIP interfa
During simulation those assertion errors are fired.
But simulation continue without fail. and getion pass status end of test.
in assertion only $error is present. I do’t wan to change those. (ie. $error → $fatal or something else).
But I wan to finish test simulation with those assertion error fired.
Is there a way for do so?