Driving a DUT input port from the testbench

UVM
,
1

I have an output design_wcomp coming out of the design. In my scoreboard, I keep a count of these to see if they match the expected value. Once they match, I need to drive an “input port” tb_design_write_done.

I do not have a sequence yet for the design_wcomp. But inside the scoreboard, I have a task that gets the transaction from a TLM analsyis fifo to count the design_wcomp.
I also have a sequencer in the agent.

With all this, how can I drive an input design port from the TB?

I tried tapping the design signal into the virtual interface and tb_top and I used config_db:: get of the vif in the SB and driving it. Although the connection seems to pass compile, the driven value is not reflected on the input port.

I see that some examples show that the design port is accessible through the sequencer which can be driven from the sequence. If this is correct implementation method,could someone please point me to a working example or idea?

2

You can have a event in the scoreboard once the condition is satisfied you can trigger that and have driver wait for it. Once driver sees the event it can drive the signal to DUT.

3

In reply to UVM_learner6:

I have an output design_wcomp coming out of the design. In my scoreboard, I keep a count of these to see if they match the expected value. Once they match, I need to drive an “input port” tb_design_write_done.
I do not have a sequence yet for the design_wcomp. But inside the scoreboard, I have a task that gets the transaction from a TLM analsyis fifo to count the design_wcomp.
I also have a sequencer in the agent.
With all this, how can I drive an input design port from the TB?
I tried tapping the design signal into the virtual interface and tb_top and I used config_db:: get of the vif in the SB and driving it. Although the connection seems to pass compile, the driven value is not reflected on the input port.
I see that some examples show that the design port is accessible through the sequencer which can be driven from the sequence. If this is correct implementation method,could someone please point me to a working example or idea?

Could you please explain how your design is starting without an input? Most designs need a certain input to prduce an output.

4

In reply to chr_sue:

In reply to UVM_learner6:
Could you please explain how your design is starting without an input? Most designs need a certain input to prduce an output.

This is a final “done” to the DUT. The DUT is already running. TB needs to mimic “done” coming from another block that is connected to DUT.

5

In reply to UVM_learner6:

It is still confusing what you are saying. Do you vahe a complete UVM testbench for your DUT? And you have to issue a signal ‘done’ under certain conditions. Then the done signal does not make any sense to have in the SB. It can be used to trigger an event indicating to the SB it should start compairing.