In reply to knowajay:
$root is a SystemVerilog construct representing the top of the static elaborated module/interface hierarchy. This hierarchy gets constructed as part of elaboration stage of the compiler and executes before any simulation starts running. I have more information about it in this blog post.
umm_root is the name of a class in the UVM library used by the root of the umm_component class hierarchy. The hierarchy gets constructed dynamically when simulation starts at time 0. The build_phase in the UVM is the class-based corresponding step to the module-based elaboration.