Design Finite State Machine Forcing

UVM
,
1

Hi,
Any possible way to force state of design finite state machine ?
Forcing operation didnt work with uvm_hdl_force , uvm_hdl_deposit vs.

Thank for help.

2

In reply to emregayir:

You need to be more descriptive about “didn’t work”. Did you get errors? Did you get result’s you were not expecting?

3

In reply to dave_59:

Hi dave,
I try to know any way of FSM forcing. Normaly I can force signals in VHDL design code with related uvm method. But during FSM state forcing process I cant do this. At related simulation time it is not get state value which I have forced .
For example.
Design part
TYPE my_fsm is (idle,state1);
signal state : my_fsm;

Verification Part
typedef enum integer {idle,state1} state_e;
state_e my_fsm;
my_fsm = state1;
uvm_hdl_force(“DUV.state”,my_fsm);

This design state dont get state1 always in idle during simulation time.

Thaks.

4

In reply to emregayir:

Unfortunately there is no standard for interoperability between standards. Please read your tools User Manual for mixed language simulation, or contact your tool vendor directly for support.