In reply to dave_59:
Hi dave,
I try to know any way of FSM forcing. Normaly I can force signals in VHDL design code with related uvm method. But during FSM state forcing process I cant do this. At related simulation time it is not get state value which I have forced .
For example.
Design part
TYPE my_fsm is (idle,state1);
signal state : my_fsm;
Verification Part
typedef enum integer {idle,state1} state_e;
state_e my_fsm;
my_fsm = state1;
uvm_hdl_force(“DUV.state”,my_fsm);
This design state dont get state1 always in idle during simulation time.
Thaks.