Can you have conditional statements inside a randomize function call

UVM
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1

Hi Guys,

I am wondering if the following can be done. Can i have a conditional check on the macro “DC__NUM1" "DC__NUM2” and based on that result, randomize with the following constraint. I am running into the following error:

Error-[SE] Syntax error
Following verilog source has syntax error :
95: token is ‘begin’
begin



    task run_phase(uvm_phase phase);
        phase.raise_objection(this);
 
        //random settings
        foreach(cfg_per_pipe[i]) begin
            if (!cfg_per_pipe[i].randomize() with {
                    UPDATE_SAMPLE_RATE_COUNT_EN == 0;
                    SAMPLE_RATE_COUNT_EN_2 == 0;
                    SAMPLE_RATE_COUNT_EN_1 == 0;
                    
**if(`DC__NUM1 != `DC__NUM2 ) begin
                    //fixed pipe setting
                    var_SOURCE_SELECT                      == i;
    end
**                
                }) `uvm_fatal(get_name(), $sformatf("cfg_per_pipe[%0d] randomization failed", i))
        end
2

In reply to rohit400:


 task run_phase(uvm_phase phase);
        phase.raise_objection(this);
 
        //random settings
        foreach(cfg_per_pipe[i]) begin
            if (!cfg_per_pipe[i].randomize() with {
                    UPDATE_SAMPLE_RATE_COUNT_EN == 0;
                    SAMPLE_RATE_COUNT_EN_2 == 0;
                    SAMPLE_RATE_COUNT_EN_1 == 0;
 
                    if(`DC__NUM1 != `DC__NUM2 ) {
                      //fixed pipe setting
                      var_SOURCE_SELECT                      == i;
                    }
                
                }) `uvm_fatal(get_name(), $sformatf("cfg_per_pipe[%0d] randomization failed", i))
        end
3

In reply to cgales:

Thank you cgales