Can I have an analysis port inside my driver ?If yes, then why we have monitor ?If no,why ?
In reply to utkalikapanda:
uvm_driver class by default has analysis port called rsp_port,
uvm_analysis_port #(RSP) rsp_port;
Which is meant to be connected to sequencer rsp_export, but it can also be connected to any other component in env. You can also have user defined analysis port in driver like any other component.
Using monitor has several reasons,
- Passive UVC: When only monitoring is needed, UVC can be made passive by disabling driver and sequencer creation.
- For easy debugging: Driver is surely driving to interface, but the value driven is going to the interface or is being overridden by any other event.
- Checks: Instead of implementing everything in driver, separate checks can be implemented in monitor for memory checking or immediate assertions. These checks are also useful in passive monitoring.
- Please add to the list if found any other advantages for separate monitoring!
In reply to mayurkubavat:
The driver should never be connected to anything other than the sequencer. Do not connect the response port to any other component. The key feature of UVM which requires a monitor is the vertical reuse of the UVC,